From 42ff36a81d8ce42cb2fb3f2edbc628447e58ee92 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Thu, 12 Jan 2023 18:45:24 +0100
Subject: synth: handle protected functions in conversion functions

---
 src/simul/simul-vhdl_simul.adb | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'src/simul')

diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb
index 14f50fad7..7d1a4312a 100644
--- a/src/simul/simul-vhdl_simul.adb
+++ b/src/simul/simul-vhdl_simul.adb
@@ -2715,7 +2715,8 @@ package body Simul.Vhdl_Simul is
       end loop;
 
       --  Call resolution function
-      Res := Exec_Resolution_Call (R.Inst, R.Func, Create_Value_Memtyp (Arr));
+      Res := Exec_Resolution_Call
+        (R.Inst, R.Func, Null_Node, Create_Value_Memtyp (Arr));
 
       --  Set driving value.
       Exec_Write_Signal (R.Sig, (Res.Typ, Res.Val.Mem),
-- 
cgit v1.2.3