From 1cc80ba8063de7083de78fc0473a1e5d6999a111 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Tue, 30 Jun 2020 18:42:53 +0200
Subject: vhdl-sem_psl: avoid a crash in synth on incorrect clock.

---
 src/psl/psl-rewrites.ads | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/psl/psl-rewrites.ads')

diff --git a/src/psl/psl-rewrites.ads b/src/psl/psl-rewrites.ads
index ac76b7805..bb1eb58bc 100644
--- a/src/psl/psl-rewrites.ads
+++ b/src/psl/psl-rewrites.ads
@@ -1,6 +1,7 @@
 with PSL.Nodes; use PSL.Nodes;
 
 package PSL.Rewrites is
+   function Rewrite_Boolean (N : Node) return Node;
    function Rewrite_SERE (N : Node) return Node;
    function Rewrite_Property (N : Node) return Node;
    procedure Rewrite_Unit (N : Node);
-- 
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