From db9df06f901abe21976ae8f5d3b680965daef70b Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Tue, 22 Mar 2016 05:34:06 +0100 Subject: PSL: add clocked SERE, make endpoints visible from VHDL. --- src/psl/psl-nodes.adb | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/psl/psl-nodes.adb') diff --git a/src/psl/psl-nodes.adb b/src/psl/psl-nodes.adb index 263994d21..d7de320a8 100644 --- a/src/psl/psl-nodes.adb +++ b/src/psl/psl-nodes.adb @@ -346,6 +346,7 @@ package body PSL.Nodes is | N_Concat_SERE | N_Fusion_SERE | N_Within_SERE + | N_Clocked_SERE | N_Overlap_Imp_Seq | N_Imp_Seq | N_And_Seq @@ -442,6 +443,7 @@ package body PSL.Nodes is | N_Concat_SERE | N_Fusion_SERE | N_Within_SERE + | N_Clocked_SERE | N_Match_And_Seq | N_And_Seq | N_Or_Seq -- cgit v1.2.3