From c8c53919d4cfad5eef122ad8a63ff9a26a7db125 Mon Sep 17 00:00:00 2001
From: 1138-4EB <1138-4EB@users.noreply.github.com>
Date: Sun, 19 Feb 2017 08:20:38 +0100
Subject: Add dots to TODOs

---
 doc/building/VendorPrimitives.rst |  2 +-
 doc/building/index.rst            |  4 ++--
 doc/changelog/index.rst           |  2 +-
 doc/getting/Releases.rst          |  2 +-
 doc/intro/Contributing.rst        |  8 +++-----
 doc/intro/Copyrights.rst          |  4 +---
 doc/intro/WhatIsVHDL.rst          |  4 +---
 doc/using/Simulation.rst          | 16 ----------------
 8 files changed, 10 insertions(+), 32 deletions(-)

(limited to 'doc')

diff --git a/doc/building/VendorPrimitives.rst b/doc/building/VendorPrimitives.rst
index 49c35b5a4..1a35838fa 100644
--- a/doc/building/VendorPrimitives.rst
+++ b/doc/building/VendorPrimitives.rst
@@ -317,7 +317,7 @@ Last update: 28.10.2016
 
 ------------------------
 
-.. TODO: topic
+.. TODO:: topic
 
   - Vendor Primitives 
     - Alters / Intel
diff --git a/doc/building/index.rst b/doc/building/index.rst
index d240ff94d..40162acb7 100644
--- a/doc/building/index.rst
+++ b/doc/building/index.rst
@@ -3,7 +3,7 @@
 Building GHDL
 #############
 
-.. TODO: topic
+.. TODO:: topic
 
   `./BUILD.txt <https://github.com/tgingold/ghdl/blob/master/BUILD.txt>`_
   Directory structure of the main branch [1138: #279]
@@ -37,6 +37,6 @@ Test suites
 
 ----------------
 
-.. TODO: topic
+.. TODO:: topic
 
   @1138 explain that there are two (maybe three with vhdl08 tests)
\ No newline at end of file
diff --git a/doc/changelog/index.rst b/doc/changelog/index.rst
index 959d68486..406641fc2 100644
--- a/doc/changelog/index.rst
+++ b/doc/changelog/index.rst
@@ -25,6 +25,6 @@ Change Log
 
 ------------------------
 
-.. TODO: topic
+.. TODO:: topic
 
   `./NEWS <https://github.com/tgingold/ghdl/blob/master/NEWS>`_
diff --git a/doc/getting/Releases.rst b/doc/getting/Releases.rst
index 0fbd4542d..7a15a4d24 100644
--- a/doc/getting/Releases.rst
+++ b/doc/getting/Releases.rst
@@ -3,6 +3,6 @@
 Releases
 ########
 
-.. TODO: topic
+.. TODO:: topic
  
   naming, stable, development, nightly
\ No newline at end of file
diff --git a/doc/intro/Contributing.rst b/doc/intro/Contributing.rst
index 8a0ba30bc..e76f83628 100644
--- a/doc/intro/Contributing.rst
+++ b/doc/intro/Contributing.rst
@@ -65,13 +65,11 @@ you have not understood some parts of this manual, please tell me.
 English is not my mother tongue, so this manual may not be well-written.
 Again, rewriting part of it is a good way to improve it.
 
----
+.. TODO:: topic
 
-@TODO:
-
-- Reporting bugs
+  - Reporting bugs
 	- [1138: Issues, search first]
 	- Minimum-(non)-Working-Example (MWE)
-- Pull Requests (PRs)
+  - Pull Requests (PRs)
 	- [1138: check chapter 2 -> building -> GHDL -> directory structure]
 	- [1138: beware that some commit messages can `automatically close <https://help.github.com/articles/closing-issues-via-commit-messages/>`_ PRs]
\ No newline at end of file
diff --git a/doc/intro/Copyrights.rst b/doc/intro/Copyrights.rst
index 06cc7e4a9..a2f15f177 100644
--- a/doc/intro/Copyrights.rst
+++ b/doc/intro/Copyrights.rst
@@ -44,9 +44,7 @@ sources.  To my mind, this is not a real restriction, since there is no
 points in distributing VHDL executable.  Please, send a comment
 (:ref:`Reporting_bugs`) if you don't like this policy.
 
-----------------
-
-.. TODO: topic
+.. TODO:: topic
 
   https://www.gnu.org/licenses/old-licenses/gpl-2.0.html
   
diff --git a/doc/intro/WhatIsVHDL.rst b/doc/intro/WhatIsVHDL.rst
index b70b3a723..852168f78 100644
--- a/doc/intro/WhatIsVHDL.rst
+++ b/doc/intro/WhatIsVHDL.rst
@@ -28,8 +28,6 @@ Like a program written in another hardware description language, a `VHDL`
 program can be transformed with a :dfn:`synthesis tool` into a netlist, that is,
 a detailed gate-level implementation.
 
-----------------
-
-.. TODO: topic
+.. TODO:: topic
 
   @1138 very very briefly explain that there are four major verions: 87, 93, 02 and 08
\ No newline at end of file
diff --git a/doc/using/Simulation.rst b/doc/using/Simulation.rst
index 73c74bcd0..041962b05 100644
--- a/doc/using/Simulation.rst
+++ b/doc/using/Simulation.rst
@@ -28,8 +28,6 @@ Here is the list of the most useful options.  Some debugging options are
 also available, but not described here.  The :option:`--help` options lists
 all options available, including the debugging one.
 
-
-
 .. option:: --assert-level=<LEVEL>
 
   Select the assertion level at which an assertion violation stops the
@@ -58,7 +56,6 @@ all options available, including the debugging one.
   This option can be useful to avoid assertion message from
   :samp:`ieee.numeric_std` (and other :samp:`ieee` packages).
 
-
 .. option:: --stop-time=<TIME>
 
   Stop the simulation after :samp:`TIME`.  :samp:`TIME` is expressed as a time
@@ -70,7 +67,6 @@ all options available, including the debugging one.
     $ ./my_design --stop-time=10ns
     $ ./my_design --stop-time=ps
 
-
 .. option:: --stop-delta=<N>
 
   Stop the simulation after `N` delta cycles in the same current time.
@@ -90,7 +86,6 @@ all options available, including the debugging one.
   This may be useful to understand the structure of a complex
   design. `KIND` is optional, but if set must be one of:
 
-
   * none
     Do not display hierarchy.  Same as if the option was not present.
 
@@ -105,19 +100,16 @@ all options available, including the debugging one.
     If `KIND` is not specified, the hierarchy is displayed with the
     :samp:`port` mode.
 
-
 .. option:: --no-run
 
   Do not simulate, only elaborate.  This may be used with
   :option:`--disp-tree` to display the tree without simulating the whole
   design.
 
-
 .. option:: --unbuffered
 
   Disable buffering on stdout, stderr and files opened in write or append mode (TEXTIO).
 
-
 .. option:: --read-opt-file=<FILENAME>
 
   Filter signals to be dumped to the wave file according to the wave option
@@ -151,14 +143,12 @@ all options available, including the debugging one.
      # those of sub3)
      /**/sub3/*/*
 
-
 .. option:: --write-opt-file=<FILENAME>
 
   If the wave option file doesn't exist, creates it with all the signals of
   the design. Otherwise throws an error, because it won't erase an existing
   file.
 
-
 .. option:: --vcd=<FILENAME>
 
 .. option:: --vcdgz=<FILENAME>
@@ -185,7 +175,6 @@ all options available, including the debugging one.
   Since it comes from `verilog`, only a few VHDL types can be dumped.  GHDL
   dumps only signals whose base type is of the following:
 
-
   * types defined in the :samp:`std.standard` package:
 
   * :samp:`bit`
@@ -213,14 +202,12 @@ all options available, including the debugging one.
   format supporting VHDL types.  If you are aware of such a free format,
   please mail me (:ref:`Reporting_bugs`).
 
-
 .. option:: --fst=<FILENAME>
 
   Write the waveforms into a `fst`, that can be displayed by
   `gtkwave`. The `fst` files are much smaller than VCD or
   `GHW` files, but it handles only the same signals as the VCD format.
 
-
 .. option:: --wave=<FILENAME>
 
   Write the waveforms into a `ghw` (GHdl Waveform) file.  Currently, all
@@ -232,14 +219,12 @@ all options available, including the debugging one.
 
   Contrary to VCD files, any VHDL type can be dumped into a GHW file.
 
-
 .. option:: --psl-report=<FILENAME>
 
   Write a report for PSL assertions and coverage at the end of
   simulation.  The file is written using the JSON format, but still
   being human readable.
 
-
 .. option:: --sdf=<PATH>=<FILENAME>
 
   Do VITAL annotation on `PATH` with SDF file :file:`FILENAME`.
@@ -261,7 +246,6 @@ all options available, including the debugging one.
 
   See :ref:`Backannotation`, for more details.
 
-
 .. option:: --help
 
   Display a short description of the options accepted by the runtime library.
-- 
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