From a1fb74c4fa69c035ea298c3d526a9a277c8db1f7 Mon Sep 17 00:00:00 2001 From: 1138-4EB <1138-4EB@users.noreply.github.com> Date: Sun, 19 Feb 2017 07:32:50 +0100 Subject: File extensions must be rst, not rst.txt --- doc/0_Intro/Copyrights.rst | 12 ++++++------ doc/0_Intro/WhatIsVHDL.rst | 6 ++++-- 2 files changed, 10 insertions(+), 8 deletions(-) (limited to 'doc/0_Intro') diff --git a/doc/0_Intro/Copyrights.rst b/doc/0_Intro/Copyrights.rst index 1684fb035..06cc7e4a9 100644 --- a/doc/0_Intro/Copyrights.rst +++ b/doc/0_Intro/Copyrights.rst @@ -44,12 +44,12 @@ sources. To my mind, this is not a real restriction, since there is no points in distributing VHDL executable. Please, send a comment (:ref:`Reporting_bugs`) if you don't like this policy. ---- +---------------- -@TODO: +.. TODO: topic -https://www.gnu.org/licenses/old-licenses/gpl-2.0.html + https://www.gnu.org/licenses/old-licenses/gpl-2.0.html + + Available in the following formats: plain text, Texinfo, LaTeX, standalone HTML, Docbook, Markdown, ODF, RT -Available in the following formats: plain text, Texinfo, LaTeX, standalone HTML, Docbook, Markdown, ODF, RT - -See `#280 `_ \ No newline at end of file + See `#280 `_ \ No newline at end of file diff --git a/doc/0_Intro/WhatIsVHDL.rst b/doc/0_Intro/WhatIsVHDL.rst index fbf0dbd73..b70b3a723 100644 --- a/doc/0_Intro/WhatIsVHDL.rst +++ b/doc/0_Intro/WhatIsVHDL.rst @@ -28,6 +28,8 @@ Like a program written in another hardware description language, a `VHDL` program can be transformed with a :dfn:`synthesis tool` into a netlist, that is, a detailed gate-level implementation. ---- +---------------- -@TODO: [1138: very very briefly explain that there are four major verions: 87, 93, 02 and 08] \ No newline at end of file +.. TODO: topic + + @1138 very very briefly explain that there are four major verions: 87, 93, 02 and 08 \ No newline at end of file -- cgit v1.2.3