From f1e3878ee7360e59e1a8d068c25b4cfd46b86e93 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Tue, 8 Oct 2019 19:14:59 +0200
Subject: synth-disp_vhdl: fix incorrect code for record of width

---
 src/synth/synth-disp_vhdl.adb | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/synth/synth-disp_vhdl.adb b/src/synth/synth-disp_vhdl.adb
index abff34d9e..319f42f05 100644
--- a/src/synth/synth-disp_vhdl.adb
+++ b/src/synth/synth-disp_vhdl.adb
@@ -166,6 +166,7 @@ package body Synth.Disp_Vhdl is
             declare
                Els : constant Node_Flist :=
                  Get_Elements_Declaration_List (Ptype);
+               Rec_Full : constant Boolean := Full and Typ.W = 1;
             begin
                for I in Flist_First .. Flist_Last (Els) loop
                   declare
@@ -176,7 +177,7 @@ package body Synth.Disp_Vhdl is
                      Disp_In_Converter
                        (Mname,
                         Pfx & '.' & Name_Table.Image (Get_Identifier (El)),
-                        Off + Et.Off, Get_Type (El), Et.Typ, False);
+                        Off + Et.Off, Get_Type (El), Et.Typ, Rec_Full);
                   end;
                end loop;
             end;
@@ -185,6 +186,7 @@ package body Synth.Disp_Vhdl is
       end case;
    end Disp_In_Converter;
 
+   --  Disp conversion for output port (so in the form wrap_i <= i).
    procedure Disp_Input_Port_Converter (Inst : Synth_Instance_Acc;
                                         Port : Node)
    is
-- 
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