From e5ce655bd182daaddb5f685f077cb69a416d34c4 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Sat, 28 Mar 2020 18:31:29 +0100 Subject: vhdl: recognize reduce functions in std_logic_misc. --- python/libghdl/thin/vhdl/nodes.py | 12 ++++ src/vhdl/vhdl-ieee-std_logic_misc.adb | 102 ++++++++++++++++++++++++++++++++++ src/vhdl/vhdl-ieee-std_logic_misc.ads | 22 ++++++++ src/vhdl/vhdl-nodes.ads | 16 +++++- src/vhdl/vhdl-post_sems.adb | 3 + 5 files changed, 154 insertions(+), 1 deletion(-) create mode 100644 src/vhdl/vhdl-ieee-std_logic_misc.adb create mode 100644 src/vhdl/vhdl-ieee-std_logic_misc.ads diff --git a/python/libghdl/thin/vhdl/nodes.py b/python/libghdl/thin/vhdl/nodes.py index 7a9b650c1..9a2a05f60 100644 --- a/python/libghdl/thin/vhdl/nodes.py +++ b/python/libghdl/thin/vhdl/nodes.py @@ -1457,6 +1457,18 @@ class Iir_Predefined: Ieee_Std_Logic_Arith_Add_Log_Uns_Slv = 474 Ieee_Std_Logic_Arith_Add_Sgn_Log_Slv = 475 Ieee_Std_Logic_Arith_Add_Log_Sgn_Slv = 476 + Ieee_Std_Logic_Misc_And_Reduce_Slv = 477 + Ieee_Std_Logic_Misc_And_Reduce_Suv = 478 + Ieee_Std_Logic_Misc_Nand_Reduce_Slv = 479 + Ieee_Std_Logic_Misc_Nand_Reduce_Suv = 480 + Ieee_Std_Logic_Misc_Or_Reduce_Slv = 481 + Ieee_Std_Logic_Misc_Or_Reduce_Suv = 482 + Ieee_Std_Logic_Misc_Nor_Reduce_Slv = 483 + Ieee_Std_Logic_Misc_Nor_Reduce_Suv = 484 + Ieee_Std_Logic_Misc_Xor_Reduce_Slv = 485 + Ieee_Std_Logic_Misc_Xor_Reduce_Suv = 486 + Ieee_Std_Logic_Misc_Xnor_Reduce_Slv = 487 + Ieee_Std_Logic_Misc_Xnor_Reduce_Suv = 488 Get_Kind = libghdl.vhdl__nodes__get_kind Get_Location = libghdl.vhdl__nodes__get_location diff --git a/src/vhdl/vhdl-ieee-std_logic_misc.adb b/src/vhdl/vhdl-ieee-std_logic_misc.adb new file mode 100644 index 000000000..5bf71405b --- /dev/null +++ b/src/vhdl/vhdl-ieee-std_logic_misc.adb @@ -0,0 +1,102 @@ +-- Nodes recognizer for ieee.std_logic_misc. +-- Copyright (C) 2020 Tristan Gingold +-- +-- GHDL is free software; you can redistribute it and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation; either version 2, or (at your option) any later +-- version. +-- +-- GHDL is distributed in the hope that it will be useful, but WITHOUT ANY +-- WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with GHDL; see the file COPYING. If not, write to the Free +-- Software Foundation, 59 Temple Place - Suite 330, Boston, MA +-- 02111-1307, USA. + +with Std_Names; use Std_Names; +with Vhdl.Errors; use Vhdl.Errors; +with Vhdl.Ieee.Std_Logic_1164; + +package body Vhdl.Ieee.Std_Logic_Misc is + Error : exception; + + procedure Extract_Declarations (Pkg : Iir_Package_Declaration) + is + Decl : Iir; + + function Handle_Reduce (Res_Slv : Iir_Predefined_Functions; + Res_Suv : Iir_Predefined_Functions) + return Iir_Predefined_Functions + is + Arg : Iir; + Arg_Type : Iir; + begin + Arg := Get_Interface_Declaration_Chain (Decl); + if Is_Null (Arg) then + raise Error; + end if; + if Get_Chain (Arg) /= Null_Iir then + raise Error; + end if; + Arg_Type := Get_Type (Arg); + if Arg_Type = Ieee.Std_Logic_1164.Std_Logic_Vector_Type then + return Res_Slv; + elsif Arg_Type = Ieee.Std_Logic_1164.Std_Ulogic_Vector_Type then + return Res_Suv; + else + raise Error; + end if; + end Handle_Reduce; + + Def : Iir_Predefined_Functions; + begin + Decl := Get_Declaration_Chain (Pkg); + + -- Handle functions. + while Is_Valid (Decl) loop + Def := Iir_Predefined_None; + + if Get_Kind (Decl) = Iir_Kind_Function_Declaration + and then Get_Implicit_Definition (Decl) = Iir_Predefined_None + then + case Get_Identifier (Decl) is + when Name_And_Reduce => + Def := Handle_Reduce + (Iir_Predefined_Ieee_Std_Logic_Misc_And_Reduce_Slv, + Iir_Predefined_Ieee_Std_Logic_Misc_And_Reduce_Suv); + when Name_Nand_Reduce => + Def := Handle_Reduce + (Iir_Predefined_Ieee_Std_Logic_Misc_Nand_Reduce_Slv, + Iir_Predefined_Ieee_Std_Logic_Misc_Nand_Reduce_Suv); + when Name_Or_Reduce => + Def := Handle_Reduce + (Iir_Predefined_Ieee_Std_Logic_Misc_Or_Reduce_Slv, + Iir_Predefined_Ieee_Std_Logic_Misc_Or_Reduce_Suv); + when Name_Nor_Reduce => + Def := Handle_Reduce + (Iir_Predefined_Ieee_Std_Logic_Misc_Nor_Reduce_Slv, + Iir_Predefined_Ieee_Std_Logic_Misc_Nor_Reduce_Suv); + when Name_Xor_Reduce => + Def := Handle_Reduce + (Iir_Predefined_Ieee_Std_Logic_Misc_Xor_Reduce_Slv, + Iir_Predefined_Ieee_Std_Logic_Misc_Xor_Reduce_Suv); + when Name_Xnor_Reduce => + Def := Handle_Reduce + (Iir_Predefined_Ieee_Std_Logic_Misc_Xnor_Reduce_Slv, + Iir_Predefined_Ieee_Std_Logic_Misc_Xnor_Reduce_Suv); + when others => + Def := Iir_Predefined_None; + end case; + Set_Implicit_Definition (Decl, Def); + end if; + + Decl := Get_Chain (Decl); + end loop; + exception + when Error => + Error_Msg_Sem (+Pkg, "package ieee.std_logic_misc is ill-formed"); + end Extract_Declarations; +end Vhdl.Ieee.Std_Logic_Misc; diff --git a/src/vhdl/vhdl-ieee-std_logic_misc.ads b/src/vhdl/vhdl-ieee-std_logic_misc.ads new file mode 100644 index 000000000..151a142a1 --- /dev/null +++ b/src/vhdl/vhdl-ieee-std_logic_misc.ads @@ -0,0 +1,22 @@ +-- Nodes recognizer for ieee.std_logic_misc +-- Copyright (C) 2020 Tristan Gingold +-- +-- GHDL is free software; you can redistribute it and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation; either version 2, or (at your option) any later +-- version. +-- +-- GHDL is distributed in the hope that it will be useful, but WITHOUT ANY +-- WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with GHDL; see the file COPYING. If not, write to the Free +-- Software Foundation, 59 Temple Place - Suite 330, Boston, MA +-- 02111-1307, USA. + +package Vhdl.Ieee.Std_Logic_Misc is + -- Extract declarations from PKG . + procedure Extract_Declarations (Pkg : Iir_Package_Declaration); +end Vhdl.Ieee.Std_Logic_Misc; diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index fb3084616..d8bcd14ec 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -5808,7 +5808,21 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Log_Slv, Iir_Predefined_Ieee_Std_Logic_Arith_Add_Log_Uns_Slv, Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Log_Slv, - Iir_Predefined_Ieee_Std_Logic_Arith_Add_Log_Sgn_Slv + Iir_Predefined_Ieee_Std_Logic_Arith_Add_Log_Sgn_Slv, + + -- std_logic_misc (synopsys extension) + Iir_Predefined_Ieee_Std_Logic_Misc_And_Reduce_Slv, + Iir_Predefined_Ieee_Std_Logic_Misc_And_Reduce_Suv, + Iir_Predefined_Ieee_Std_Logic_Misc_Nand_Reduce_Slv, + Iir_Predefined_Ieee_Std_Logic_Misc_Nand_Reduce_Suv, + Iir_Predefined_Ieee_Std_Logic_Misc_Or_Reduce_Slv, + Iir_Predefined_Ieee_Std_Logic_Misc_Or_Reduce_Suv, + Iir_Predefined_Ieee_Std_Logic_Misc_Nor_Reduce_Slv, + Iir_Predefined_Ieee_Std_Logic_Misc_Nor_Reduce_Suv, + Iir_Predefined_Ieee_Std_Logic_Misc_Xor_Reduce_Slv, + Iir_Predefined_Ieee_Std_Logic_Misc_Xor_Reduce_Suv, + Iir_Predefined_Ieee_Std_Logic_Misc_Xnor_Reduce_Slv, + Iir_Predefined_Ieee_Std_Logic_Misc_Xnor_Reduce_Suv ); -- Return TRUE iff FUNC is a short-cut predefined function. diff --git a/src/vhdl/vhdl-post_sems.adb b/src/vhdl/vhdl-post_sems.adb index 8924a1d45..5477a3136 100644 --- a/src/vhdl/vhdl-post_sems.adb +++ b/src/vhdl/vhdl-post_sems.adb @@ -24,6 +24,7 @@ with Vhdl.Ieee.Numeric; with Vhdl.Ieee.Math_Real; with Vhdl.Ieee.Std_Logic_Unsigned; with Vhdl.Ieee.Std_Logic_Arith; +with Vhdl.Ieee.Std_Logic_Misc; with Flags; use Flags; package body Vhdl.Post_Sems is @@ -70,6 +71,8 @@ package body Vhdl.Post_Sems is (Lib_Unit, Vhdl.Ieee.Std_Logic_Unsigned.Pkg_Signed); when Name_Std_Logic_Arith => Vhdl.Ieee.Std_Logic_Arith.Extract_Declarations (Lib_Unit); + when Name_Std_Logic_Misc => + Vhdl.Ieee.Std_Logic_Misc.Extract_Declarations (Lib_Unit); when others => null; end case; -- cgit v1.2.3