From e2a988ff5777dc81708842676564e3fa32a2b910 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Tue, 30 Jul 2019 20:58:03 +0200
Subject: synth: add a counter test.

---
 testsuite/synth/cnt01/cnt01.vhdl    | 35 ++++++++++++++++++++
 testsuite/synth/cnt01/tb_cnt01.vhdl | 66 +++++++++++++++++++++++++++++++++++++
 testsuite/synth/cnt01/testsuite.sh  | 16 +++++++++
 3 files changed, 117 insertions(+)
 create mode 100644 testsuite/synth/cnt01/cnt01.vhdl
 create mode 100644 testsuite/synth/cnt01/tb_cnt01.vhdl
 create mode 100755 testsuite/synth/cnt01/testsuite.sh

diff --git a/testsuite/synth/cnt01/cnt01.vhdl b/testsuite/synth/cnt01/cnt01.vhdl
new file mode 100644
index 000000000..371cf604b
--- /dev/null
+++ b/testsuite/synth/cnt01/cnt01.vhdl
@@ -0,0 +1,35 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity cnt01 is
+  port (
+    clock       : in STD_LOGIC;
+    reset       : in STD_LOGIC;
+
+    clear_count : in STD_LOGIC;
+    enable      : in STD_LOGIC;
+
+    counter_out : out STD_LOGIC_VECTOR (9 downto 0)
+    );
+end cnt01;
+
+architecture behav of cnt01 is
+  signal s_count : unsigned(9 downto 0); -- := (others => '0');
+begin
+  process(clock, reset)
+  begin
+    if reset = '1' then
+      s_count <= (others => '0');
+    elsif rising_edge(clock) then
+      if clear_count = '1' then
+        s_count <= (others => '0');
+      elsif enable = '1' then
+        s_count <= s_count + 1;
+      end if;
+    end if;
+  end process;
+
+  -- connect internal signal to output
+  counter_out <= std_logic_vector(s_count);
+end behav;
diff --git a/testsuite/synth/cnt01/tb_cnt01.vhdl b/testsuite/synth/cnt01/tb_cnt01.vhdl
new file mode 100644
index 000000000..8e3035521
--- /dev/null
+++ b/testsuite/synth/cnt01/tb_cnt01.vhdl
@@ -0,0 +1,66 @@
+entity tb_cnt01 is
+end tb_cnt01;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_cnt01 is
+  signal clk : std_logic;
+  signal rst : std_logic;
+  signal clr : std_logic;
+  signal en : std_logic;
+  signal cnt : std_logic_vector (9 downto 0);
+begin
+  dut: entity work.cnt01
+    port map (clock => clk, reset => rst, clear_count => clr,
+              enable => en, counter_out => cnt);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    clk <= '0';
+    clr <= '0';
+    en <= '0';
+    rst <= '1';
+    wait for 1 ns;
+    assert cnt = "0000000000" severity failure;
+
+    rst <= '0';
+    pulse;
+    assert cnt = "0000000000" severity failure;
+
+    en <= '1';
+    pulse;
+    assert cnt = "0000000001" severity failure;
+
+    en <= '0';
+    pulse;
+    assert cnt = "0000000001" severity failure;
+
+    en <= '1';
+    pulse;
+    assert cnt = "0000000010" severity failure;
+
+    en <= '1';
+    pulse;
+    assert cnt = "0000000011" severity failure;
+
+    en <= '1';
+    clr <= '1';
+    pulse;
+    assert cnt = "0000000000" severity failure;
+
+    en <= '1';
+    clr <= '0';
+    pulse;
+    assert cnt = "0000000001" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/cnt01/testsuite.sh b/testsuite/synth/cnt01/testsuite.sh
new file mode 100755
index 000000000..e791a3dcb
--- /dev/null
+++ b/testsuite/synth/cnt01/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in cnt01; do
+    analyze $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+done
+
+echo "Test successful"
-- 
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