From e18e9569ee6748f46bea65eccd078f3d4f2cee22 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sun, 1 Nov 2020 18:42:27 +0100
Subject: testsuite/synth: add testcase for #1503

---
 testsuite/synth/issue1503/testsuite.sh |  7 +++++++
 testsuite/synth/issue1503/theunit.vhdl | 22 ++++++++++++++++++++++
 2 files changed, 29 insertions(+)
 create mode 100755 testsuite/synth/issue1503/testsuite.sh
 create mode 100644 testsuite/synth/issue1503/theunit.vhdl

diff --git a/testsuite/synth/issue1503/testsuite.sh b/testsuite/synth/issue1503/testsuite.sh
new file mode 100755
index 000000000..080c84be1
--- /dev/null
+++ b/testsuite/synth/issue1503/testsuite.sh
@@ -0,0 +1,7 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth theunit.vhdl -e
+
+echo "Test successful"
diff --git a/testsuite/synth/issue1503/theunit.vhdl b/testsuite/synth/issue1503/theunit.vhdl
new file mode 100644
index 000000000..a8b2e0b3c
--- /dev/null
+++ b/testsuite/synth/issue1503/theunit.vhdl
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+entity theunit is
+  port (a : in  std_ulogic);
+end;
+
+architecture rtl of theunit is
+begin
+  comb : process (a)
+    variable c : natural range 0 to 3;
+    variable d : std_ulogic_vector(3 downto 0);
+  begin
+    if a = '1' then
+      for i in 0 to 2 loop
+        exit;
+      end loop;
+    end if;
+    c := 0;
+    d := (others => '0');
+    d(c) := '1';
+  end process;
+end;
-- 
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