From db9c1fd3700995155b2d8a32d929b3d0dc9689e2 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Fri, 12 Jun 2020 07:47:46 +0200 Subject: vhdl: analyze and synth concurrent statements in vunit. Fix #1366 --- python/libghdl/thin/vhdl/nodes.py | 5 +++++ src/synth/synth-stmts.adb | 7 ++++++- src/vhdl/vhdl-annotations.adb | 7 ++++++- src/vhdl/vhdl-canon.adb | 19 ++++++++++++------- src/vhdl/vhdl-nodes.ads | 5 +++++ src/vhdl/vhdl-sem_psl.adb | 19 ++++++++++++------- 6 files changed, 46 insertions(+), 16 deletions(-) diff --git a/python/libghdl/thin/vhdl/nodes.py b/python/libghdl/thin/vhdl/nodes.py index 04aa11dcb..e25d2ef95 100644 --- a/python/libghdl/thin/vhdl/nodes.py +++ b/python/libghdl/thin/vhdl/nodes.py @@ -496,6 +496,11 @@ class Iir_Kinds: Iir_Kind.Psl_Rose, Iir_Kind.Psl_Fell] + Generate_Statement = [ + Iir_Kind.If_Generate_Statement, + Iir_Kind.Case_Generate_Statement, + Iir_Kind.For_Generate_Statement] + Composite_Subtype_Definition = [ Iir_Kind.Array_Subtype_Definition, Iir_Kind.Record_Subtype_Definition] diff --git a/src/synth/synth-stmts.adb b/src/synth/synth-stmts.adb index a7b8dc232..cdc5290a4 100644 --- a/src/synth/synth-stmts.adb +++ b/src/synth/synth-stmts.adb @@ -3650,7 +3650,12 @@ package body Synth.Stmts is | Iir_Kind_Attribute_Declaration | Iir_Kind_Attribute_Specification => Synth_Declaration (Unit_Inst, Item, False, Last_Type); - when Iir_Kind_Concurrent_Simple_Signal_Assignment => + when Iir_Kinds_Concurrent_Signal_Assignment + | Iir_Kinds_Process_Statement + | Iir_Kinds_Generate_Statement + | Iir_Kind_Block_Statement + | Iir_Kind_Concurrent_Procedure_Call_Statement + | Iir_Kind_Component_Instantiation_Statement => Synth_Concurrent_Statement (Unit_Inst, Item); when others => Error_Kind ("synth_verification_unit", Item); diff --git a/src/vhdl/vhdl-annotations.adb b/src/vhdl/vhdl-annotations.adb index 4ec3e8849..20cfe9737 100644 --- a/src/vhdl/vhdl-annotations.adb +++ b/src/vhdl/vhdl-annotations.adb @@ -1155,7 +1155,12 @@ package body Vhdl.Annotations is | Iir_Kind_Attribute_Declaration | Iir_Kind_Attribute_Specification => Annotate_Declaration (Vunit_Info, Item); - when Iir_Kind_Concurrent_Simple_Signal_Assignment => + when Iir_Kinds_Concurrent_Signal_Assignment + | Iir_Kinds_Process_Statement + | Iir_Kinds_Generate_Statement + | Iir_Kind_Block_Statement + | Iir_Kind_Concurrent_Procedure_Call_Statement + | Iir_Kind_Component_Instantiation_Statement => Annotate_Concurrent_Statement (Vunit_Info, Item); when others => Error_Kind ("annotate_vunit_declaration", Item); diff --git a/src/vhdl/vhdl-canon.adb b/src/vhdl/vhdl-canon.adb index 90ef9cac6..319a329a6 100644 --- a/src/vhdl/vhdl-canon.adb +++ b/src/vhdl/vhdl-canon.adb @@ -3435,14 +3435,19 @@ package body Vhdl.Canon is when Iir_Kind_Psl_Cover_Directive => Canon_Psl_Cover_Directive (Item); when Iir_Kind_Signal_Declaration - | Iir_Kind_Function_Declaration - | Iir_Kind_Procedure_Declaration - | Iir_Kind_Function_Body - | Iir_Kind_Procedure_Body - | Iir_Kind_Attribute_Declaration - | Iir_Kind_Attribute_Specification => + | Iir_Kind_Function_Declaration + | Iir_Kind_Procedure_Declaration + | Iir_Kind_Function_Body + | Iir_Kind_Procedure_Body + | Iir_Kind_Attribute_Declaration + | Iir_Kind_Attribute_Specification => Item := Canon_Declaration (Unit, Item, Null_Iir); - when Iir_Kind_Concurrent_Simple_Signal_Assignment => + when Iir_Kinds_Concurrent_Signal_Assignment + | Iir_Kinds_Process_Statement + | Iir_Kinds_Generate_Statement + | Iir_Kind_Block_Statement + | Iir_Kind_Concurrent_Procedure_Call_Statement + | Iir_Kind_Component_Instantiation_Statement => Canon_Concurrent_Label (Item, Proc_Num); Canon_Concurrent_Statement (Item, Unit); when others => diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 05cbcf576..014520cf4 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -6664,6 +6664,11 @@ package Vhdl.Nodes is --Iir_Kind_Psl_Cover_Directive Iir_Kind_Psl_Restrict_Directive; + subtype Iir_Kinds_Generate_Statement is Iir_Kind range + Iir_Kind_If_Generate_Statement .. + --Iir_Kind_Case_Generate_Statement + Iir_Kind_For_Generate_Statement; + subtype Iir_Kinds_Concurrent_Signal_Assignment is Iir_Kind range Iir_Kind_Concurrent_Simple_Signal_Assignment .. --Iir_Kind_Concurrent_Conditional_Signal_Assignment diff --git a/src/vhdl/vhdl-sem_psl.adb b/src/vhdl/vhdl-sem_psl.adb index 290e13836..e4b3554fd 100644 --- a/src/vhdl/vhdl-sem_psl.adb +++ b/src/vhdl/vhdl-sem_psl.adb @@ -1195,15 +1195,20 @@ package body Vhdl.Sem_Psl is when Iir_Kind_Psl_Cover_Directive => Sem_Psl_Cover_Directive (Item); when Iir_Kind_Signal_Declaration - | Iir_Kind_Function_Declaration - | Iir_Kind_Procedure_Declaration - | Iir_Kind_Function_Body - | Iir_Kind_Procedure_Body - | Iir_Kind_Attribute_Declaration - | Iir_Kind_Attribute_Specification => + | Iir_Kind_Function_Declaration + | Iir_Kind_Procedure_Declaration + | Iir_Kind_Function_Body + | Iir_Kind_Procedure_Body + | Iir_Kind_Attribute_Declaration + | Iir_Kind_Attribute_Specification => Sem_Decls.Sem_Declaration (Item, Prev_Item, False, Attr_Spec_Chain); - when Iir_Kind_Concurrent_Simple_Signal_Assignment => + when Iir_Kinds_Concurrent_Signal_Assignment + | Iir_Kinds_Process_Statement + | Iir_Kinds_Generate_Statement + | Iir_Kind_Block_Statement + | Iir_Kind_Concurrent_Procedure_Call_Statement + | Iir_Kind_Component_Instantiation_Statement => Sem_Stmts.Sem_Concurrent_Statement (Item, False); when others => Error_Kind ("sem_psl_verification_unit", Item); -- cgit v1.2.3