From da51617af9e574ec595b128c03e5cb842ec3f0c2 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Wed, 21 Apr 2021 20:42:06 +0200
Subject: testsuite/synth: add a test for #1731

---
 testsuite/synth/issue1731/ent.vhdl     | 20 ++++++++++++++++++++
 testsuite/synth/issue1731/testsuite.sh |  4 ++++
 2 files changed, 24 insertions(+)
 create mode 100644 testsuite/synth/issue1731/ent.vhdl

diff --git a/testsuite/synth/issue1731/ent.vhdl b/testsuite/synth/issue1731/ent.vhdl
new file mode 100644
index 000000000..8170f1f86
--- /dev/null
+++ b/testsuite/synth/issue1731/ent.vhdl
@@ -0,0 +1,20 @@
+library ieee;
+context ieee.ieee_std_context;
+
+entity ent is
+  port (
+    dsin  : in signed(15 downto 0);
+    dsout : out signed(31 downto 0);
+    duin  : in unsigned(15 downto 0);
+    duout : out unsigned(31 downto 0)
+  );
+end;
+
+architecture arch of ent is
+
+begin
+
+  dsout <= resize(signed(dsin), dsout);
+  duout <= resize(unsigned(duin), duout);
+
+end architecture;
diff --git a/testsuite/synth/issue1731/testsuite.sh b/testsuite/synth/issue1731/testsuite.sh
index 557967b15..196cc2b74 100755
--- a/testsuite/synth/issue1731/testsuite.sh
+++ b/testsuite/synth/issue1731/testsuite.sh
@@ -6,6 +6,10 @@ GHDL_STD_FLAGS=--std=08
 synth -gfifo_depth=3 fifo.vhdl axis_conv1d9x1.vhdl -e > syn_axi_conv1d9x1.vhdl
 
 analyze syn_axi_conv1d9x1.vhdl
+
+synth ent.vhdl -e > syn_ent.vhdl
+analyze syn_ent.vhdl
+
 clean
 
 echo "Test successful"
-- 
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