From d8cd7bc8a47e283028c7f90ece2e768f7bfb4fa6 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Thu, 23 Apr 2020 07:48:18 +0200
Subject: testsuite/synth: add a test for ghdl/ghdl-yosys-plugin#110

---
 testsuite/synth/synth110/testsuite.sh | 10 ++++++++++
 testsuite/synth/synth110/top.vhdl     | 27 +++++++++++++++++++++++++++
 2 files changed, 37 insertions(+)
 create mode 100755 testsuite/synth/synth110/testsuite.sh
 create mode 100644 testsuite/synth/synth110/top.vhdl

diff --git a/testsuite/synth/synth110/testsuite.sh b/testsuite/synth/synth110/testsuite.sh
new file mode 100755
index 000000000..63190913e
--- /dev/null
+++ b/testsuite/synth/synth110/testsuite.sh
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_analyze top
+grep "if rising_edge" syn_top.vhdl
+
+clean
+
+echo "Test successful"
diff --git a/testsuite/synth/synth110/top.vhdl b/testsuite/synth/synth110/top.vhdl
new file mode 100644
index 000000000..aec306ea2
--- /dev/null
+++ b/testsuite/synth/synth110/top.vhdl
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity top is
+    port(
+        clk  : in  std_logic;
+	di   : in  std_logic;
+        do   : out std_logic
+    ); 
+end top;
+
+architecture behavioral of top is
+    signal data : std_logic;
+begin
+
+    mylabel: process (clk)
+        variable tmp : std_logic;
+    begin
+        if rising_edge(clk) then
+            tmp := di;              -- Post-synthesis name : mylabel.tmp
+        end if;
+        data <= not(tmp);           
+    end process;
+
+    do <= not(data);
+    
+end behavioral;
-- 
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