From d6c71f92412036657c423572e34550b0a733c3fc Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sat, 17 Jul 2021 18:57:51 +0200
Subject: testsuite/gna: add a test for #1818

---
 testsuite/gna/issue1818/mwe.vhdl     | 22 ++++++++++++++++++++++
 testsuite/gna/issue1818/testsuite.sh | 11 +++++++++++
 2 files changed, 33 insertions(+)
 create mode 100644 testsuite/gna/issue1818/mwe.vhdl
 create mode 100755 testsuite/gna/issue1818/testsuite.sh

diff --git a/testsuite/gna/issue1818/mwe.vhdl b/testsuite/gna/issue1818/mwe.vhdl
new file mode 100644
index 000000000..ee8da01a4
--- /dev/null
+++ b/testsuite/gna/issue1818/mwe.vhdl
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity ghdl_mwe is
+port
+(
+    o_ArrayElementSize : out Natural
+);
+end entity ghdl_mwe;
+
+architecture RTL of ghdl_mwe is
+
+type t_TestArray is array (0 to 3) of std_logic_vector(8-1 downto 0);
+constant TestArray : t_TestArray := (x"00", x"01", x"02", x"03");
+    
+begin
+
+    o_ArrayElementSize <= TestArray'Element'Length;
+
+end architecture RTL;
+
diff --git a/testsuite/gna/issue1818/testsuite.sh b/testsuite/gna/issue1818/testsuite.sh
new file mode 100755
index 000000000..cc00c7de0
--- /dev/null
+++ b/testsuite/gna/issue1818/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze mwe.vhdl
+elab_simulate ghdl_mwe
+
+clean
+
+echo "Test successful"
-- 
cgit v1.2.3