From d10b226f3d1dc302d7a95b9c2d77beaece3d3634 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Tue, 20 Jul 2021 07:38:35 +0200 Subject: testsuite/gna: add a test for #1817 --- testsuite/gna/issue1817/full_adder.vhdl | 67 +++++++++++++++++ testsuite/gna/issue1817/full_adder_tb.vhdl | 112 +++++++++++++++++++++++++++++ testsuite/gna/issue1817/testsuite.sh | 29 ++++++++ 3 files changed, 208 insertions(+) create mode 100644 testsuite/gna/issue1817/full_adder.vhdl create mode 100644 testsuite/gna/issue1817/full_adder_tb.vhdl create mode 100755 testsuite/gna/issue1817/testsuite.sh diff --git a/testsuite/gna/issue1817/full_adder.vhdl b/testsuite/gna/issue1817/full_adder.vhdl new file mode 100644 index 000000000..ca24cf5d7 --- /dev/null +++ b/testsuite/gna/issue1817/full_adder.vhdl @@ -0,0 +1,67 @@ +------------------------------------------------------------------------------- +-- Title : Full-Adder +-- Project : +------------------------------------------------------------------------------- +--! \file full_adder.vhd +--! \author Jose Correcher +--! \date Created : 2021-07-02 +-- Last update: 2021-07-02 +-- Platform : +-- Standard : VHDL'08 +------------------------------------------------------------------------------- +-- Description: +--! \class full_adder +--! \details +--! This core contains a full-adder design. +------------------------------------------------------------------------------- +-- Copyright (c) 2021 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2021-07-02 1.0 jcorrecher Created +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- * libraries +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +------------------------------------------------------------------------------- +-- * entity +------------------------------------------------------------------------------- + +entity full_adder is + + port ( + a : in std_logic; + b : in std_logic; + cin : in std_logic; + s : out std_logic; + cout : out std_logic); + +end entity full_adder; + +------------------------------------------------------------------------------- +-- * architecture body +------------------------------------------------------------------------------- + +architecture rtl of full_adder is + +begin + +------------------------------------------------------------------------------- +-- * result +------------------------------------------------------------------------------- + + res_assign: s <= (a xor b) xor cin; + +------------------------------------------------------------------------------- +-- * carry out +------------------------------------------------------------------------------- + + cout_assign: cout <= ((a xor b) and cin) or (a and b); + +end architecture rtl; diff --git a/testsuite/gna/issue1817/full_adder_tb.vhdl b/testsuite/gna/issue1817/full_adder_tb.vhdl new file mode 100644 index 000000000..0e49c4f18 --- /dev/null +++ b/testsuite/gna/issue1817/full_adder_tb.vhdl @@ -0,0 +1,112 @@ +------------------------------------------------------------------------------- +-- Title : Full-Adder Test Bench +-- Project : +------------------------------------------------------------------------------- +--! \file full_adder_tb.vhd +--! \author Jose Correcher +--! \date Created : 2021-07-02 +-- Last update: 2021-07-02 +-- Platform : +-- Standard : VHDL'08 +------------------------------------------------------------------------------- +-- Description: +--! \class full_adder +--! \details +--! This is the test bench for full-adder design. +------------------------------------------------------------------------------- +-- Copyright (c) 2021 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2021-07-02 1.0 jcorrecher Created +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- * libraries +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +------------------------------------------------------------------------------- +-- * entity +------------------------------------------------------------------------------- + +entity full_adder_tb is + +end entity full_adder_tb; + +------------------------------------------------------------------------------- +-- * architecture body +------------------------------------------------------------------------------- + +architecture sim of full_adder_tb is + +-- ** record declaration + type rc_data is record + a : std_logic; + b : std_logic; + cin : std_logic; + s : std_logic; + cout : std_logic; + end record rc_data; + +-- ** truth table declaration + type fa_array is array (natural range <>) of rc_data; + constant fa_table : fa_array := + (('0', '0', '0', '0', '0'), + ('0', '0', '1', '1', '0'), + ('0', '1', '0', '1', '0'), + ('0', '1', '1', '0', '1'), + ('1', '0', '0', '1', '0'), + ('1', '0', '1', '0', '1'), + ('1', '1', '0', '0', '1'), + ('1', '1', '1', '1', '1')); + +-- ** signal declaration + signal a, b, cin, s, cout : std_logic; + +begin + +------------------------------------------------------------------------------- +-- * TB0 : Test +------------------------------------------------------------------------------- + + process + begin + -- Check each pattern. + for i in fa_table'range loop + -- Set the inputs. + a <= fa_table(i).a; + b <= fa_table(i).b; + cin <= fa_table(i).cin; + -- Wait for the results. + wait for 1 ns; + -- Check the outputs. + assert s = fa_table(i).s + report "bad sum value" severity error; + assert cout = fa_table(i).cout + report "bad carry out value" severity error; + end loop; + assert false report "end of test" severity note; + std.env.stop; + wait; + end process; + +------------------------------------------------------------------------------- +-- * TB1 : DUV + FM +------------------------------------------------------------------------------- + +-- ** instance + + DUV : entity work.full_adder + port map ( + a => a, + b => b, + cin => cin, + s => s, + cout => cout + ); + +end architecture sim; diff --git a/testsuite/gna/issue1817/testsuite.sh b/testsuite/gna/issue1817/testsuite.sh new file mode 100755 index 000000000..5c20675ca --- /dev/null +++ b/testsuite/gna/issue1817/testsuite.sh @@ -0,0 +1,29 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=--std=08 + +if $GHDL --version | grep -q "GCC back-end code"; then + is_gcc=true +else + is_gcc=false +fi + +if [ "$is_gcc" = true ]; then + GHDL_FLAGS="-fprofile-arcs -ftest-coverage -Wl,--coverage" +fi + +analyze full_adder.vhdl +analyze full_adder_tb.vhdl + +# Do not try to elaborate, libgcov may not be available + +if [ "$is_gcc" = true ]; then + test -f full_adder.gcno + test -f full_adder_tb.gcno +fi + +clean + +echo "Test successful" -- cgit v1.2.3