From d00af0f399558b6d0d7e84ec58050921a0648204 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Mon, 18 Jan 2021 19:22:04 +0100 Subject: testsuite/gna: add testcase for #1612 --- testsuite/gna/issue1612/exposep.vhdl | 24 ++++++++++++++++++++++++ testsuite/gna/issue1612/repro.vhdl | 28 ++++++++++++++++++++++++++++ testsuite/gna/issue1612/testsuite.sh | 10 ++++++++++ 3 files changed, 62 insertions(+) create mode 100644 testsuite/gna/issue1612/exposep.vhdl create mode 100644 testsuite/gna/issue1612/repro.vhdl create mode 100755 testsuite/gna/issue1612/testsuite.sh diff --git a/testsuite/gna/issue1612/exposep.vhdl b/testsuite/gna/issue1612/exposep.vhdl new file mode 100644 index 000000000..1078d2865 --- /dev/null +++ b/testsuite/gna/issue1612/exposep.vhdl @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity expose_problem is + port ( + arg : in std_logic_vector); +end entity; + +library ieee; +use ieee.std_logic_1164.all; + +entity expose is + generic ( + ARG : std_logic_vector); +end entity; + +architecture rtl of expose is + +begin + expose_problem_1 : entity work.expose_problem + port map ( + arg => ARG + ); +end architecture; diff --git a/testsuite/gna/issue1612/repro.vhdl b/testsuite/gna/issue1612/repro.vhdl new file mode 100644 index 000000000..cf884522b --- /dev/null +++ b/testsuite/gna/issue1612/repro.vhdl @@ -0,0 +1,28 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity expose_problem is + port ( + arg : in std_logic_vector); +end entity; + +architecture behav of expose_problem is +begin +end behav; + +library ieee; +use ieee.std_logic_1164.all; + +entity expose is + generic ( + ARG : std_logic_vector := x"56"); +end entity; + +architecture rtl of expose is + +begin + expose_problem_1 : entity work.expose_problem + port map ( + arg => ARG + ); +end architecture; diff --git a/testsuite/gna/issue1612/testsuite.sh b/testsuite/gna/issue1612/testsuite.sh new file mode 100755 index 000000000..2d3f46835 --- /dev/null +++ b/testsuite/gna/issue1612/testsuite.sh @@ -0,0 +1,10 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze repro.vhdl +elab_simulate expose + +clean + +echo "Test successful" -- cgit v1.2.3