From cd4acc3e0237fbc658696835d0901d0a2a0355d1 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Mon, 5 Dec 2016 03:23:56 +0100
Subject: Add testcase for type interface.

---
 testsuite/gna/bug065/repro.vhdl   | 17 +++++++++++++++++
 testsuite/gna/bug065/testsuite.sh | 11 +++++++++++
 2 files changed, 28 insertions(+)
 create mode 100644 testsuite/gna/bug065/repro.vhdl
 create mode 100755 testsuite/gna/bug065/testsuite.sh

diff --git a/testsuite/gna/bug065/repro.vhdl b/testsuite/gna/bug065/repro.vhdl
new file mode 100644
index 000000000..70035bbd3
--- /dev/null
+++ b/testsuite/gna/bug065/repro.vhdl
@@ -0,0 +1,17 @@
+package gen is
+  generic (type t);
+end gen;
+
+entity e is
+end entity;
+
+library ieee;
+use     ieee.std_logic_1164.all;
+
+architecture a of e is
+  subtype T_DATA		is std_logic_vector(31 downto 0);
+  type T_DATA_VECTOR		is array(natural range <>) of T_DATA;
+
+  package pkg is new work.gen generic map (t => t_data_vector);
+begin
+end architecture;
diff --git a/testsuite/gna/bug065/testsuite.sh b/testsuite/gna/bug065/testsuite.sh
new file mode 100755
index 000000000..f4a473727
--- /dev/null
+++ b/testsuite/gna/bug065/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze repro.vhdl
+elab_simulate e
+
+clean
+
+echo "Test successful"
-- 
cgit v1.2.3