From ccee381c7e7a028e61ebfb03dc8e80047a1d6b54 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Mon, 7 Nov 2022 07:56:27 +0100
Subject: testsuite/gna: add a test for previous commit

---
 testsuite/gna/bug0134/test_logic.vhdl | 42 +++++++++++++++++++++++++++++++++++
 testsuite/gna/bug0134/testsuite.sh    | 10 +++++++++
 2 files changed, 52 insertions(+)
 create mode 100644 testsuite/gna/bug0134/test_logic.vhdl
 create mode 100755 testsuite/gna/bug0134/testsuite.sh

diff --git a/testsuite/gna/bug0134/test_logic.vhdl b/testsuite/gna/bug0134/test_logic.vhdl
new file mode 100644
index 000000000..2f8a45e0f
--- /dev/null
+++ b/testsuite/gna/bug0134/test_logic.vhdl
@@ -0,0 +1,42 @@
+entity test_logic is
+   port(
+      a, b, c, d : in  bit;
+      g : out bit
+   );
+end test_logic;
+
+architecture structure of test_logic is
+    -- function "not" (i: bit) return bit is
+    -- begin
+    --     if i = '1' then
+    --         return '0';
+    --     else
+    --         return '1';
+    --     end if;
+  -- end function "not";
+  component AND1
+    port(s, t : in bit;
+         u : out bit
+         );
+  end component;
+  component OR1
+    port(x, y, z : in bit;
+         n : out bit
+         );
+  end component;
+  signal e, k, h : bit;
+begin
+    x1: AND1 port map(s => "not"(a),
+          t => "not"(d),
+          u => e);
+    x2: AND1 port map(s => "not"(b),
+          t => "not"(d),
+          u => k);
+    x3: AND1 port map(s => a,
+          t => d,
+          u => h);
+    x4: OR1 port map(x => e,
+           y => k,
+           z => h,
+           n => g);
+end structure;
diff --git a/testsuite/gna/bug0134/testsuite.sh b/testsuite/gna/bug0134/testsuite.sh
new file mode 100755
index 000000000..e2ee40cdf
--- /dev/null
+++ b/testsuite/gna/bug0134/testsuite.sh
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze test_logic.vhdl
+elab_simulate test_logic
+
+clean
+
+echo "Test successful"
-- 
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