From e95d45e41d32c0d73179cea22c8b3ea812eafb41 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Thu, 13 Apr 2023 23:44:29 +0200 Subject: Reworking symbols. --- pyGHDL/dom/Attribute.py | 4 +-- pyGHDL/dom/Concurrent.py | 32 +++++++++------------ pyGHDL/dom/DesignUnit.py | 8 +++--- pyGHDL/dom/Expression.py | 6 ++-- pyGHDL/dom/Sequential.py | 19 ++++++------- pyGHDL/dom/Symbol.py | 72 +++++++++++++++++++----------------------------- pyGHDL/dom/_Translate.py | 29 ++++++++++--------- pyGHDL/dom/_Utils.py | 47 ++++++------------------------- 8 files changed, 81 insertions(+), 136 deletions(-) diff --git a/pyGHDL/dom/Attribute.py b/pyGHDL/dom/Attribute.py index 7133c86a2..7dcb7b1ef 100644 --- a/pyGHDL/dom/Attribute.py +++ b/pyGHDL/dom/Attribute.py @@ -45,7 +45,7 @@ from pyGHDL.libghdl.vhdl import nodes from pyGHDL.libghdl.vhdl.tokens import Tok from pyGHDL.dom import DOMMixin, Position, DOMException, Expression from pyGHDL.dom._Utils import GetNameOfNode, GetIirKindOfNode, GetDocumentationOfNode -from pyGHDL.dom._Translate import GetNameFromNode, GetExpressionFromNode +from pyGHDL.dom._Translate import GetName, GetExpressionFromNode from pyGHDL.dom.Names import SimpleName from pyGHDL.dom.Symbol import SimpleSubtypeSymbol @@ -109,7 +109,7 @@ class AttributeSpecification(VHDLModel_AttributeSpecification, DOMMixin): @classmethod def parse(cls, attributeNode: Iir) -> "AttributeSpecification": attributeDesignator = nodes.Get_Attribute_Designator(attributeNode) - attributeName = GetNameFromNode(attributeDesignator) + attributeName = GetName(attributeDesignator) documentation = GetDocumentationOfNode(attributeNode) names = [] diff --git a/pyGHDL/dom/Concurrent.py b/pyGHDL/dom/Concurrent.py index 3b3c06f2e..71ee634cc 100644 --- a/pyGHDL/dom/Concurrent.py +++ b/pyGHDL/dom/Concurrent.py @@ -70,12 +70,6 @@ from pyVHDLModel.Concurrent import ( from pyGHDL.libghdl import Iir, utils from pyGHDL.libghdl.vhdl import nodes from pyGHDL.dom import DOMMixin, DOMException, Position -from pyGHDL.dom._Utils import ( - GetNameOfNode, - GetEntityInstantiationSymbol, - GetComponentInstantiationSymbol, - GetConfigurationInstantiationSymbol, -) from pyGHDL.dom.Range import Range from pyGHDL.dom.Symbol import ( ArchitectureSymbol, @@ -146,7 +140,7 @@ class EntityInstantiation(VHDLModel_EntityInstantiation, DOMMixin): @classmethod def parse(cls, instantiationNode: Iir, instantiatedUnit: Iir, label: str) -> "EntityInstantiation": - from pyGHDL.dom._Translate import GetGenericMapAspect, GetPortMapAspect + from pyGHDL.dom._Translate import GetName, GetGenericMapAspect, GetPortMapAspect entityId = nodes.Get_Entity_Name(instantiatedUnit) entitySymbol = GetEntityInstantiationSymbol(entityId) @@ -154,7 +148,7 @@ class EntityInstantiation(VHDLModel_EntityInstantiation, DOMMixin): architectureSymbol = None architectureId = nodes.Get_Architecture(instantiatedUnit) if architectureId != nodes.Null_Iir: - architectureSymbol = ArchitectureSymbol(GetNameOfNode(architectureId), entitySymbol) + architectureSymbol = ArchitectureSymbol(GetName(architectureId), entitySymbol) genericAssociations = GetGenericMapAspect(nodes.Get_Generic_Map_Aspect_Chain(instantiationNode)) portAssociations = GetPortMapAspect(nodes.Get_Port_Map_Aspect_Chain(instantiationNode)) @@ -230,13 +224,13 @@ class ProcessStatement(VHDLModel_ProcessStatement, DOMMixin): @classmethod def parse(cls, processNode: Iir, label: str, hasSensitivityList: bool) -> "ProcessStatement": - from pyGHDL.dom._Translate import GetDeclaredItemsFromChainedNodes, GetSequentialStatementsFromChainedNodes + from pyGHDL.dom._Translate import GetName, GetDeclaredItemsFromChainedNodes, GetSequentialStatementsFromChainedNodes sensitivityList = None if hasSensitivityList: sensitivityList = [] for item in utils.list_iter(nodes.Get_Sensitivity_List(processNode)): - sensitivityList.append(GetNameOfNode(item)) + sensitivityList.append(GetName(item)) declaredItems = GetDeclaredItemsFromChainedNodes(nodes.Get_Declaration_Chain(processNode), "process", label) statements = GetSequentialStatementsFromChainedNodes( @@ -490,7 +484,7 @@ class CaseGenerateStatement(VHDLModel_CaseGenerateStatement, DOMMixin): from pyGHDL.dom._Translate import ( GetExpressionFromNode, GetRangeFromNode, - GetNameFromNode, + GetName, ) expression = GetExpressionFromNode(nodes.Get_Expression(generateNode)) @@ -524,7 +518,7 @@ class CaseGenerateStatement(VHDLModel_CaseGenerateStatement, DOMMixin): nodes.Iir_Kind.Attribute_Name, nodes.Iir_Kind.Parenthesis_Name, ): - rng = GetNameFromNode(choiceRange) + rng = GetName(choiceRange) else: pos = Position.parse(alternative) raise DOMException( @@ -585,11 +579,11 @@ class ForGenerateStatement(VHDLModel_ForGenerateStatement, DOMMixin): GetDeclaredItemsFromChainedNodes, GetConcurrentStatementsFromChainedNodes, GetRangeFromNode, - GetNameFromNode, + GetName, ) spec = nodes.Get_Parameter_Specification(generateNode) - loopIndex = GetNameOfNode(spec) + loopIndex = GetName(spec) discreteRange = nodes.Get_Discrete_Range(spec) rangeKind = GetIirKindOfNode(discreteRange) @@ -599,7 +593,7 @@ class ForGenerateStatement(VHDLModel_ForGenerateStatement, DOMMixin): nodes.Iir_Kind.Attribute_Name, nodes.Iir_Kind.Parenthesis_Name, ): - rng = GetNameFromNode(discreteRange) + rng = GetName(discreteRange) else: pos = Position.parse(generateNode) raise DOMException( @@ -651,10 +645,10 @@ class ConcurrentSimpleSignalAssignment(VHDLModel_ConcurrentSimpleSignalAssignmen @classmethod def parse(cls, assignmentNode: Iir, label: str) -> "ConcurrentSimpleSignalAssignment": - from pyGHDL.dom._Translate import GetNameFromNode + from pyGHDL.dom._Translate import GetName target = nodes.Get_Target(assignmentNode) - targetName = GetNameFromNode(target) + targetName = GetName(target) waveform = [] for wave in utils.chain_iter(nodes.Get_Waveform_Chain(assignmentNode)): @@ -677,12 +671,12 @@ class ConcurrentProcedureCall(VHDLModel_ConcurrentProcedureCall, DOMMixin): @classmethod def parse(cls, concurrentCallNode: Iir, label: str) -> "ConcurrentProcedureCall": - from pyGHDL.dom._Translate import GetNameFromNode, GetParameterMapAspect + from pyGHDL.dom._Translate import GetName, GetParameterMapAspect callNode = nodes.Get_Procedure_Call(concurrentCallNode) prefix = nodes.Get_Prefix(callNode) - procedureName = GetNameFromNode(prefix) + procedureName = GetName(prefix) parameterAssociations = GetParameterMapAspect(nodes.Get_Parameter_Association_Chain(callNode)) return cls(concurrentCallNode, label, procedureName, parameterAssociations) diff --git a/pyGHDL/dom/DesignUnit.py b/pyGHDL/dom/DesignUnit.py index 079364742..6484d1532 100644 --- a/pyGHDL/dom/DesignUnit.py +++ b/pyGHDL/dom/DesignUnit.py @@ -63,8 +63,8 @@ from pyGHDL.libghdl import utils from pyGHDL.libghdl._types import Iir from pyGHDL.libghdl.vhdl import nodes from pyGHDL.dom import DOMMixin, Position, DOMException -from pyGHDL.dom._Utils import GetNameOfNode, GetDocumentationOfNode, GetPackageMemberSymbol, GetContextSymbol -from pyGHDL.dom._Translate import GetGenericsFromChainedNodes, GetPortsFromChainedNodes +from pyGHDL.dom._Utils import GetNameOfNode, GetDocumentationOfNode, GetPackageMemberSymbol +from pyGHDL.dom._Translate import GetGenericsFromChainedNodes, GetPortsFromChainedNodes, GetName from pyGHDL.dom._Translate import GetDeclaredItemsFromChainedNodes, GetConcurrentStatementsFromChainedNodes from pyGHDL.dom.Symbol import EntitySymbol, ContextReferenceSymbol, LibraryReferenceSymbol, PackageSymbol @@ -158,7 +158,7 @@ class Architecture(VHDLModel_Architecture, DOMMixin): name = GetNameOfNode(architectureNode) documentation = GetDocumentationOfNode(architectureNode) entityNameNode = nodes.Get_Entity_Name(architectureNode) - entitySymbol = EntitySymbol(entityNameNode, GetNameOfNode(entityNameNode)) + entitySymbol = EntitySymbol(entityNameNode, GetName(entityNameNode)) declaredItems = GetDeclaredItemsFromChainedNodes( nodes.Get_Declaration_Chain(architectureNode), "architecture", name ) @@ -241,7 +241,7 @@ class PackageBody(VHDLModel_PackageBody, DOMMixin): @classmethod def parse(cls, packageBodyNode: Iir, contextItems: Iterable[VHDLModel_ContextUnion]): - packageName = GetNameOfNode(packageBodyNode) + packageName = GetName(packageBodyNode) packageSymbol = PackageSymbol(packageBodyNode, packageName) documentation = GetDocumentationOfNode(packageBodyNode) declaredItems = GetDeclaredItemsFromChainedNodes( diff --git a/pyGHDL/dom/Expression.py b/pyGHDL/dom/Expression.py index 608801af6..0d8dbfba7 100644 --- a/pyGHDL/dom/Expression.py +++ b/pyGHDL/dom/Expression.py @@ -488,7 +488,7 @@ class Aggregate(VHDLModel_Aggregate, DOMMixin): from pyGHDL.dom._Translate import ( GetExpressionFromNode, GetRangeFromNode, - GetNameFromNode, + GetName, ) choices = [] @@ -512,7 +512,7 @@ class Aggregate(VHDLModel_Aggregate, DOMMixin): nodes.Iir_Kind.Attribute_Name, nodes.Iir_Kind.Parenthesis_Name, ): - rng = GetNameFromNode(choiceRange) + rng = GetName(choiceRange) else: pos = Position.parse(item) raise DOMException( @@ -521,7 +521,7 @@ class Aggregate(VHDLModel_Aggregate, DOMMixin): choices.append(RangedAggregateElement(item, rng, value)) elif kind == nodes.Iir_Kind.Choice_By_Name: - name = GetNameFromNode(nodes.Get_Choice_Name(item)) + name = GetName(nodes.Get_Choice_Name(item)) symbol = Symbol(item, name) choices.append(NamedAggregateElement(item, symbol, value)) elif kind == nodes.Iir_Kind.Choice_By_Others: diff --git a/pyGHDL/dom/Sequential.py b/pyGHDL/dom/Sequential.py index d1396941e..f289ae969 100644 --- a/pyGHDL/dom/Sequential.py +++ b/pyGHDL/dom/Sequential.py @@ -58,7 +58,6 @@ from pyVHDLModel.Sequential import SequentialAssertStatement as VHDLModel_Sequen from pyGHDL.libghdl import Iir, utils from pyGHDL.libghdl.vhdl import nodes from pyGHDL.dom import DOMMixin, Position, DOMException -from pyGHDL.dom._Utils import GetNameOfNode from pyGHDL.dom.Range import Range from pyGHDL.dom.Concurrent import WaveformElement, ParameterAssociationItem # TODO: move out from concurrent? @@ -247,7 +246,7 @@ class CaseStatement(VHDLModel_CaseStatement, DOMMixin): from pyGHDL.dom._Translate import ( GetExpressionFromNode, GetRangeFromNode, - GetNameFromNode, + GetName, ) expression = GetExpressionFromNode(nodes.Get_Expression(caseNode)) @@ -281,7 +280,7 @@ class CaseStatement(VHDLModel_CaseStatement, DOMMixin): nodes.Iir_Kind.Attribute_Name, nodes.Iir_Kind.Parenthesis_Name, ): - rng = GetNameFromNode(choiceRange) + rng = GetName(choiceRange) else: pos = Position.parse(alternative) raise DOMException( @@ -340,11 +339,11 @@ class ForLoopStatement(VHDLModel_ForLoopStatement, DOMMixin): from pyGHDL.dom._Translate import ( GetSequentialStatementsFromChainedNodes, GetRangeFromNode, - GetNameFromNode, + GetName, ) spec = nodes.Get_Parameter_Specification(loopNode) - loopIndex = GetNameOfNode(spec) + loopIndex = GetName(spec) discreteRange = nodes.Get_Discrete_Range(spec) rangeKind = GetIirKindOfNode(discreteRange) @@ -354,7 +353,7 @@ class ForLoopStatement(VHDLModel_ForLoopStatement, DOMMixin): nodes.Iir_Kind.Attribute_Name, nodes.Iir_Kind.Parenthesis_Name, ): - rng = GetNameFromNode(discreteRange) + rng = GetName(discreteRange) else: pos = Position.parse(loopNode) raise DOMException( @@ -381,10 +380,10 @@ class SequentialSimpleSignalAssignment(VHDLModel_SequentialSimpleSignalAssignmen @classmethod def parse(cls, assignmentNode: Iir, label: str = None) -> "SequentialSimpleSignalAssignment": - from pyGHDL.dom._Translate import GetNameFromNode + from pyGHDL.dom._Translate import GetName target = nodes.Get_Target(assignmentNode) - targetName = GetNameFromNode(target) + targetName = GetName(target) waveform = [] for wave in utils.chain_iter(nodes.Get_Waveform_Chain(assignmentNode)): @@ -407,12 +406,12 @@ class SequentialProcedureCall(VHDLModel_SequentialProcedureCall, DOMMixin): @classmethod def parse(cls, callNode: Iir, label: str) -> "SequentialProcedureCall": - from pyGHDL.dom._Translate import GetNameFromNode, GetParameterMapAspect + from pyGHDL.dom._Translate import GetName, GetParameterMapAspect cNode = nodes.Get_Procedure_Call(callNode) prefix = nodes.Get_Prefix(cNode) - procedureName = GetNameFromNode(prefix) + procedureName = GetName(prefix) parameterAssociations = GetParameterMapAspect(nodes.Get_Parameter_Association_Chain(cNode)) return cls(callNode, procedureName, parameterAssociations, label) diff --git a/pyGHDL/dom/Symbol.py b/pyGHDL/dom/Symbol.py index e62ec4137..7c29acf06 100644 --- a/pyGHDL/dom/Symbol.py +++ b/pyGHDL/dom/Symbol.py @@ -61,88 +61,72 @@ from pyGHDL.dom.Range import Range @export class LibraryReferenceSymbol(VHDLModel_LibraryReferenceSymbol, DOMMixin): @InheritDocString(VHDLModel_LibraryReferenceSymbol) - def __init__(self, identifierNode: Iir, identifier: str): - super().__init__(identifier) + def __init__(self, identifierNode: Iir, name: Name): + super().__init__(name) DOMMixin.__init__(self, identifierNode) @export class PackageReferenceSymbol(VHDLModel_PackageReferenceSymbol, DOMMixin): @InheritDocString(VHDLModel_PackageReferenceSymbol) - def __init__(self, identifierNode: Iir, identifier: str, prefix: LibraryReferenceSymbol): - super().__init__(identifier, prefix) - DOMMixin.__init__(self, identifierNode) - - -@export -class PackageMembersReferenceSymbol(VHDLModel_PackageMembersReferenceSymbol, DOMMixin): - @InheritDocString(VHDLModel_PackageMembersReferenceSymbol) - def __init__(self, identifierNode: Iir, identifier: str, prefix: PackageReferenceSymbol): - super().__init__(identifier, prefix) - DOMMixin.__init__(self, identifierNode) - - -@export -class AllPackageMembersReferenceSymbol(VHDLModel_AllPackageMembersReferenceSymbol, DOMMixin): - @InheritDocString(VHDLModel_AllPackageMembersReferenceSymbol) - def __init__(self, identifierNode: Iir, prefix: PackageReferenceSymbol): - super().__init__(prefix) + def __init__(self, identifierNode: Iir, name: Name): + super().__init__(name) DOMMixin.__init__(self, identifierNode) @export class ContextReferenceSymbol(VHDLModel_ContextReferenceSymbol, DOMMixin): @InheritDocString(VHDLModel_ContextReferenceSymbol) - def __init__(self, identifierNode: Iir, identifier: str, prefix: LibraryReferenceSymbol): - super().__init__(identifier, prefix) + def __init__(self, identifierNode: Iir, name: Name): + super().__init__(name) DOMMixin.__init__(self, identifierNode) @export class EntityInstantiationSymbol(VHDLModel_EntityInstantiationSymbol, DOMMixin): @InheritDocString(VHDLModel_EntityInstantiationSymbol) - def __init__(self, identifierNode: Iir, identifier: str, prefix: LibraryReferenceSymbol): - super().__init__(identifier, prefix) + def __init__(self, identifierNode: Iir, name: Name): + super().__init__(name) DOMMixin.__init__(self, identifierNode) @export class ComponentInstantiationSymbol(VHDLModel_ComponentInstantiationSymbol, DOMMixin): @InheritDocString(VHDLModel_ComponentInstantiationSymbol) - def __init__(self, identifierNode: Iir, identifier: str): - super().__init__(identifier) + def __init__(self, identifierNode: Iir, name: Name): + super().__init__(name) DOMMixin.__init__(self, identifierNode) @export class ConfigurationInstantiationSymbol(VHDLModel_ConfigurationInstantiationSymbol, DOMMixin): @InheritDocString(VHDLModel_ConfigurationInstantiationSymbol) - def __init__(self, identifierNode: Iir, identifier: str): - super().__init__(identifier) + def __init__(self, identifierNode: Iir, name: Name): + super().__init__(name) DOMMixin.__init__(self, identifierNode) @export class EntitySymbol(VHDLModel_EntitySymbol, DOMMixin): @InheritDocString(VHDLModel_EntitySymbol) - def __init__(self, identifierNode: Iir, identifier: str): - super().__init__(identifier) + def __init__(self, identifierNode: Iir, name: Name): + super().__init__(name) DOMMixin.__init__(self, identifierNode) @export class ArchitectureSymbol(VHDLModel_ArchitectureSymbol, DOMMixin): @InheritDocString(VHDLModel_ArchitectureSymbol) - def __init__(self, identifierNode: Iir, identifier: str, prefix: EntitySymbol): - super().__init__(identifier, prefix) + def __init__(self, identifierNode: Iir, name: Name): + super().__init__(name) DOMMixin.__init__(self, identifierNode) @export class PackageSymbol(VHDLModel_PackageSymbol, DOMMixin): @InheritDocString(VHDLModel_PackageSymbol) - def __init__(self, identifierNode: Iir, identifier: str): - super().__init__(identifier) + def __init__(self, identifierNode: Iir, name: Name): + super().__init__(name) DOMMixin.__init__(self, identifierNode) @@ -184,29 +168,29 @@ class ConstrainedCompositeSubtypeSymbol(VHDLModel_ConstrainedCompositeSubtypeSym @export class SimpleObjectOrFunctionCallSymbol(VHDLModel_SimpleObjectOrFunctionCallSymbol, DOMMixin): - def __init__(self, node: Iir, identifier: str): - super().__init__(identifier) + def __init__(self, node: Iir, name: Name): + super().__init__(name) DOMMixin.__init__(self, node) @classmethod def parse(cls, node: Iir): - from pyGHDL.dom._Translate import GetNameFromNode + from pyGHDL.dom._Translate import GetName - name = GetNameFromNode(node) + name = GetName(node) - return cls(node, str(name)) # XXX: hacked + return cls(node, name) @export class IndexedObjectOrFunctionCallSymbol(VHDLModel_IndexedObjectOrFunctionCallSymbol, DOMMixin): - def __init__(self, node: Iir, prefix: Name, indices: Iterable[ExpressionUnion]): - super().__init__(prefix, indices) + def __init__(self, node: Iir, name: Name): + super().__init__(name) DOMMixin.__init__(self, node) @classmethod def parse(cls, node: Iir): - from pyGHDL.dom._Translate import GetNameFromNode + from pyGHDL.dom._Translate import GetName - name = GetNameFromNode(node) + name = GetName(node) - return cls(node, name, []) + return cls(node, name) diff --git a/pyGHDL/dom/_Translate.py b/pyGHDL/dom/_Translate.py index 9ccc05158..8ab6283b2 100644 --- a/pyGHDL/dom/_Translate.py +++ b/pyGHDL/dom/_Translate.py @@ -166,26 +166,25 @@ from pyGHDL.dom.PSL import DefaultClock @export -def GetNameFromNode(node: Iir) -> Name: +def GetName(node: Iir) -> Name: kind = GetIirKindOfNode(node) if kind == nodes.Iir_Kind.Simple_Name: name = GetNameOfNode(node) return SimpleName(node, name) elif kind == nodes.Iir_Kind.Selected_Name: name = GetNameOfNode(node) - prefixName = GetNameFromNode(nodes.Get_Prefix(node)) + prefixName = GetName(nodes.Get_Prefix(node)) return SelectedName(node, name, prefixName) - elif kind == nodes.Iir_Kind.Attribute_Name: - name = GetNameOfNode(node) - prefixName = GetNameFromNode(nodes.Get_Prefix(node)) - return AttributeName(node, name, prefixName) elif kind == nodes.Iir_Kind.Parenthesis_Name: - prefixName = GetNameFromNode(nodes.Get_Prefix(node)) + prefixName = GetName(nodes.Get_Prefix(node)) associations = GetAssociations(node) - return ParenthesisName(node, prefixName, associations) + elif kind == nodes.Iir_Kind.Attribute_Name: + name = GetNameOfNode(node) + prefixName = GetName(nodes.Get_Prefix(node)) + return AttributeName(node, name, prefixName) elif kind == nodes.Iir_Kind.Selected_By_All_Name: - prefixName = GetNameFromNode(nodes.Get_Prefix(node)) + prefixName = GetName(nodes.Get_Prefix(node)) return AllName(node, prefixName) else: raise DOMException(f"Unknown name kind '{kind.name}'") @@ -227,7 +226,7 @@ def GetArrayConstraintsFromSubtypeIndication( nodes.Iir_Kind.Selected_Name, nodes.Iir_Kind.Attribute_Name, ): - constraints.append(GetNameFromNode(constraint)) + constraints.append(GetName(constraint)) else: position = Position.parse(constraint) raise DOMException( @@ -277,7 +276,7 @@ def GetAnonymousTypeFromNode(node: Iir) -> BaseType: return IntegerType(node, typeName, r) elif kind in (nodes.Iir_Kind.Attribute_Name, nodes.Iir_Kind.Parenthesis_Name): - n = GetNameFromNode(typeDefinition) + n = GetName(typeDefinition) return IntegerType(node, typeName, n) elif kind == nodes.Iir_Kind.Physical_Type_Definition: @@ -322,7 +321,7 @@ def GetSubtypeIndicationFromIndicationNode(subtypeIndicationNode: Iir, entity: s @export def GetSimpleTypeFromNode(subtypeIndicationNode: Iir) -> SimpleSubtypeSymbol: - subtypeName = GetNameFromNode(subtypeIndicationNode) + subtypeName = GetName(subtypeIndicationNode) return SimpleSubtypeSymbol(subtypeIndicationNode, str(subtypeName)) # XXX: hacked @@ -353,7 +352,7 @@ def GetCompositeConstrainedSubtypeFromNode( simpleTypeMark = SimpleName(typeMark, typeMarkName) constraints = GetArrayConstraintsFromSubtypeIndication(subtypeIndicationNode) - return ConstrainedCompositeSubtypeSymbol(subtypeIndicationNode, str(simpleTypeMark), constraints) # XXX: hacked + return ConstrainedCompositeSubtypeSymbol(subtypeIndicationNode, simpleTypeMark, constraints) @export @@ -609,7 +608,7 @@ def GetMapAspect(mapAspect: Iir, cls: Type, entity: str) -> Generator[Associatio if formalNode is nodes.Null_Iir: formal = None else: - formal = GetNameFromNode(formalNode) + formal = GetName(formalNode) actual = GetExpressionFromNode(nodes.Get_Actual(generic)) @@ -619,7 +618,7 @@ def GetMapAspect(mapAspect: Iir, cls: Type, entity: str) -> Generator[Associatio if formalNode is nodes.Null_Iir: formal = None else: - formal = GetNameFromNode(formalNode) + formal = GetName(formalNode) yield cls(generic, OpenName(generic), formal) else: diff --git a/pyGHDL/dom/_Utils.py b/pyGHDL/dom/_Utils.py index 7ab02ace9..5a9c1c135 100644 --- a/pyGHDL/dom/_Utils.py +++ b/pyGHDL/dom/_Utils.py @@ -35,23 +35,15 @@ from typing import Union from pyTooling.Decorators import export from pyVHDLModel.Base import Mode +from pyVHDLModel.Name import Name +from pyVHDLModel.Symbol import PackageMembersReferenceSymbol, AllPackageMembersReferenceSymbol from pyGHDL.libghdl import LibGHDLException, name_table, errorout_memory, files_map, file_comments from pyGHDL.libghdl._types import Iir from pyGHDL.libghdl.vhdl import nodes, utils from pyGHDL.libghdl.vhdl.nodes import Null_Iir from pyGHDL.dom import DOMException, Position -from pyGHDL.dom.Symbol import ( - LibraryReferenceSymbol, - PackageReferenceSymbol, - PackageMembersReferenceSymbol, - AllPackageMembersReferenceSymbol, - ContextReferenceSymbol, - EntityInstantiationSymbol, - ComponentInstantiationSymbol, - ConfigurationInstantiationSymbol, -) - +from pyGHDL.dom.Names import SelectedName, AllName, SimpleName __MODE_TRANSLATION = { nodes.Iir_Mode.In_Mode: Mode.In, @@ -172,35 +164,12 @@ def GetPackageSymbol(node: Iir) -> PackageReferenceSymbol: def GetPackageMemberSymbol( node: Iir, -) -> Union[PackageReferenceSymbol, PackageMembersReferenceSymbol, AllPackageMembersReferenceSymbol]: - kind = GetIirKindOfNode(node) - prefixName = GetPackageSymbol(nodes.Get_Prefix(node)) - if kind == nodes.Iir_Kind.Selected_Name: - name = GetNameOfNode(node) - return PackageMembersReferenceSymbol(node, name, prefixName) - elif kind == nodes.Iir_Kind.Selected_By_All_Name: - prefixName = GetPackageSymbol(nodes.Get_Prefix(node)) - return AllPackageMembersReferenceSymbol(node, prefixName) - else: - raise DOMException(f"{kind.name} at {Position.parse(node)}") - +) -> Union[PackageMembersReferenceSymbol, AllPackageMembersReferenceSymbol]: + from pyGHDL.dom._Translate import GetName -def GetContextSymbol(node: Iir) -> ContextReferenceSymbol: - kind = GetIirKindOfNode(node) - if kind == nodes.Iir_Kind.Selected_Name: - name = GetNameOfNode(node) - prefixName = GetLibrarySymbol(nodes.Get_Prefix(node)) - return ContextReferenceSymbol(node, name, prefixName) - else: - raise DOMException(f"{kind.name} at {Position.parse(node)}") - - -def GetEntityInstantiationSymbol(node: Iir) -> EntityInstantiationSymbol: - kind = GetIirKindOfNode(node) - if kind == nodes.Iir_Kind.Selected_Name: - name = GetNameOfNode(node) - prefixName = GetLibrarySymbol(nodes.Get_Prefix(node)) - return EntityInstantiationSymbol(node, name, prefixName) + name = GetName(node) + if isinstance(name, AllName): + return AllPackageMembersReferenceSymbol(name) else: raise DOMException(f"{kind.name} at {Position.parse(node)}") -- cgit v1.2.3 From bee2616e7fed89c042f79592ddfafa2f6aea451e Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Fri, 14 Apr 2023 07:42:22 +0200 Subject: Fixes due to failing testcases. --- pyGHDL/dom/Concurrent.py | 14 +++++++------- pyGHDL/dom/DesignUnit.py | 14 +++++++++----- pyGHDL/dom/Symbol.py | 8 ++++++++ pyGHDL/dom/Type.py | 4 ++-- 4 files changed, 26 insertions(+), 14 deletions(-) diff --git a/pyGHDL/dom/Concurrent.py b/pyGHDL/dom/Concurrent.py index 71ee634cc..4ffba28d1 100644 --- a/pyGHDL/dom/Concurrent.py +++ b/pyGHDL/dom/Concurrent.py @@ -115,9 +115,9 @@ class ComponentInstantiation(VHDLModel_ComponentInstantiation, DOMMixin): @classmethod def parse(cls, instantiationNode: Iir, instantiatedUnit: Iir, label: str) -> "ComponentInstantiation": - from pyGHDL.dom._Translate import GetGenericMapAspect, GetPortMapAspect + from pyGHDL.dom._Translate import GetName, GetGenericMapAspect, GetPortMapAspect - componentSymbol = GetComponentInstantiationSymbol(instantiatedUnit) + componentSymbol = ComponentInstantiationSymbol(instantiatedUnit, GetName(instantiatedUnit)) genericAssociations = GetGenericMapAspect(nodes.Get_Generic_Map_Aspect_Chain(instantiationNode)) portAssociations = GetPortMapAspect(nodes.Get_Port_Map_Aspect_Chain(instantiationNode)) @@ -142,8 +142,8 @@ class EntityInstantiation(VHDLModel_EntityInstantiation, DOMMixin): def parse(cls, instantiationNode: Iir, instantiatedUnit: Iir, label: str) -> "EntityInstantiation": from pyGHDL.dom._Translate import GetName, GetGenericMapAspect, GetPortMapAspect - entityId = nodes.Get_Entity_Name(instantiatedUnit) - entitySymbol = GetEntityInstantiationSymbol(entityId) + entityName = nodes.Get_Entity_Name(instantiatedUnit) + entitySymbol = EntityInstantiationSymbol(entityName, GetName(entityName)) architectureSymbol = None architectureId = nodes.Get_Architecture(instantiatedUnit) @@ -171,10 +171,10 @@ class ConfigurationInstantiation(VHDLModel_ConfigurationInstantiation, DOMMixin) @classmethod def parse(cls, instantiationNode: Iir, instantiatedUnit: Iir, label: str) -> "ConfigurationInstantiation": - from pyGHDL.dom._Translate import GetGenericMapAspect, GetPortMapAspect + from pyGHDL.dom._Translate import GetName, GetGenericMapAspect, GetPortMapAspect - configurationId = nodes.Get_Configuration_Name(instantiatedUnit) - configurationSymbol = GetConfigurationInstantiationSymbol(configurationId) + configurationName = nodes.Get_Configuration_Name(instantiatedUnit) + configurationSymbol = ConfigurationInstantiationSymbol(configurationName, GetName(configurationName)) genericAssociations = GetGenericMapAspect(nodes.Get_Generic_Map_Aspect_Chain(instantiationNode)) portAssociations = GetPortMapAspect(nodes.Get_Port_Map_Aspect_Chain(instantiationNode)) diff --git a/pyGHDL/dom/DesignUnit.py b/pyGHDL/dom/DesignUnit.py index 6484d1532..ef1a37493 100644 --- a/pyGHDL/dom/DesignUnit.py +++ b/pyGHDL/dom/DesignUnit.py @@ -66,7 +66,7 @@ from pyGHDL.dom import DOMMixin, Position, DOMException from pyGHDL.dom._Utils import GetNameOfNode, GetDocumentationOfNode, GetPackageMemberSymbol from pyGHDL.dom._Translate import GetGenericsFromChainedNodes, GetPortsFromChainedNodes, GetName from pyGHDL.dom._Translate import GetDeclaredItemsFromChainedNodes, GetConcurrentStatementsFromChainedNodes -from pyGHDL.dom.Symbol import EntitySymbol, ContextReferenceSymbol, LibraryReferenceSymbol, PackageSymbol +from pyGHDL.dom.Symbol import EntitySymbol, ContextReferenceSymbol, LibraryReferenceSymbol, PackageSymbol, PackageMemberReferenceSymbol @export @@ -84,9 +84,11 @@ class UseClause(VHDLModel_UseClause, DOMMixin): @classmethod def parse(cls, useNode: Iir): - uses = [GetPackageMemberSymbol(nodes.Get_Selected_Name(useNode))] + nameNode = nodes.Get_Selected_Name(useNode) + uses = [PackageMemberReferenceSymbol(nameNode, GetName(nameNode))] for use in utils.chain_iter(nodes.Get_Use_Clause_Chain(useNode)): - uses.append(GetPackageMemberSymbol(nodes.Get_Selected_Name(use))) + nameNode = nodes.Get_Selected_Name(use) + uses.append(PackageMemberReferenceSymbol(nameNode, GetName(nameNode))) return cls(useNode, uses) @@ -99,9 +101,11 @@ class ContextReference(VHDLModel_ContextReference, DOMMixin): @classmethod def parse(cls, contextNode: Iir): - contexts = [GetContextSymbol(nodes.Get_Selected_Name(contextNode))] + nameNode = nodes.Get_Selected_Name(contextNode) + contexts = [ContextReferenceSymbol(nameNode, GetName(nameNode))] for context in utils.chain_iter(nodes.Get_Context_Reference_Chain(contextNode)): - contexts.append(GetContextSymbol(nodes.Get_Selected_Name(context))) + nameNode = nodes.Get_Selected_Name(context) + contexts.append(ContextReferenceSymbol(nameNode, GetName(nameNode))) return cls(contextNode, contexts) diff --git a/pyGHDL/dom/Symbol.py b/pyGHDL/dom/Symbol.py index 7c29acf06..fe3f3bbe0 100644 --- a/pyGHDL/dom/Symbol.py +++ b/pyGHDL/dom/Symbol.py @@ -82,6 +82,14 @@ class ContextReferenceSymbol(VHDLModel_ContextReferenceSymbol, DOMMixin): DOMMixin.__init__(self, identifierNode) +@export +class PackageMemberReferenceSymbol(VHDLModel_PackageMembersReferenceSymbol, DOMMixin): + @InheritDocString(VHDLModel_PackageMembersReferenceSymbol) + def __init__(self, identifierNode: Iir, name: Name): + super().__init__(name) + DOMMixin.__init__(self, identifierNode) + + @export class EntityInstantiationSymbol(VHDLModel_EntityInstantiationSymbol, DOMMixin): @InheritDocString(VHDLModel_EntityInstantiationSymbol) diff --git a/pyGHDL/dom/Type.py b/pyGHDL/dom/Type.py index e7d9701fd..7df1ad7a1 100644 --- a/pyGHDL/dom/Type.py +++ b/pyGHDL/dom/Type.py @@ -114,7 +114,7 @@ class PhysicalType(VHDLModel_PhysicalType, DOMMixin): @classmethod def parse(cls, typeName: str, typeDefinitionNode: Iir) -> "PhysicalType": from pyGHDL.dom._Utils import GetIirKindOfNode, GetNameOfNode - from pyGHDL.dom._Translate import GetRangeFromNode, GetNameFromNode + from pyGHDL.dom._Translate import GetRangeFromNode, GetName rangeConstraint = nodes.Get_Range_Constraint(typeDefinitionNode) rangeKind = GetIirKindOfNode(rangeConstraint) @@ -124,7 +124,7 @@ class PhysicalType(VHDLModel_PhysicalType, DOMMixin): nodes.Iir_Kind.Attribute_Name, nodes.Iir_Kind.Parenthesis_Name, ): - rng = GetNameFromNode(rangeConstraint) + rng = GetName(rangeConstraint) else: pos = Position.parse(typeDefinitionNode) raise DOMException(f"Unknown range kind '{rangeKind.name}' in physical type definition at line {pos.Line}.") -- cgit v1.2.3 From d67bfa80c0c7d013a99636d7959cf433000ab2e7 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sat, 15 Apr 2023 10:43:09 +0200 Subject: Modifications due to changes in Symbols. --- pyGHDL/dom/Attribute.py | 2 +- pyGHDL/dom/Concurrent.py | 4 ++-- pyGHDL/dom/DesignUnit.py | 9 +++++---- pyGHDL/dom/NonStandard.py | 3 ++- pyGHDL/dom/Sequential.py | 4 ++-- pyGHDL/dom/Subprogram.py | 3 ++- pyGHDL/dom/Symbol.py | 10 ++++++---- pyGHDL/dom/Type.py | 3 ++- pyGHDL/dom/_Translate.py | 4 ++-- 9 files changed, 24 insertions(+), 18 deletions(-) diff --git a/pyGHDL/dom/Attribute.py b/pyGHDL/dom/Attribute.py index 7dcb7b1ef..08295817d 100644 --- a/pyGHDL/dom/Attribute.py +++ b/pyGHDL/dom/Attribute.py @@ -63,7 +63,7 @@ class Attribute(VHDLModel_Attribute, DOMMixin): subtypeMark = nodes.Get_Type_Mark(attributeNode) subtypeName = GetNameOfNode(subtypeMark) - subtype = SimpleSubtypeSymbol(subtypeMark, subtypeName) + subtype = SimpleSubtypeSymbol(subtypeMark, SimpleName(subtypeName)) return cls(attributeNode, name, subtype, documentation) diff --git a/pyGHDL/dom/Concurrent.py b/pyGHDL/dom/Concurrent.py index 4ffba28d1..303b6b96b 100644 --- a/pyGHDL/dom/Concurrent.py +++ b/pyGHDL/dom/Concurrent.py @@ -574,7 +574,7 @@ class ForGenerateStatement(VHDLModel_ForGenerateStatement, DOMMixin): @classmethod def parse(cls, generateNode: Iir, label: str) -> "ForGenerateStatement": - from pyGHDL.dom._Utils import GetIirKindOfNode + from pyGHDL.dom._Utils import GetIirKindOfNode, GetNameOfNode from pyGHDL.dom._Translate import ( GetDeclaredItemsFromChainedNodes, GetConcurrentStatementsFromChainedNodes, @@ -583,7 +583,7 @@ class ForGenerateStatement(VHDLModel_ForGenerateStatement, DOMMixin): ) spec = nodes.Get_Parameter_Specification(generateNode) - loopIndex = GetName(spec) + loopIndex = GetNameOfNode(spec) discreteRange = nodes.Get_Discrete_Range(spec) rangeKind = GetIirKindOfNode(discreteRange) diff --git a/pyGHDL/dom/DesignUnit.py b/pyGHDL/dom/DesignUnit.py index ef1a37493..9779a7ea0 100644 --- a/pyGHDL/dom/DesignUnit.py +++ b/pyGHDL/dom/DesignUnit.py @@ -66,6 +66,7 @@ from pyGHDL.dom import DOMMixin, Position, DOMException from pyGHDL.dom._Utils import GetNameOfNode, GetDocumentationOfNode, GetPackageMemberSymbol from pyGHDL.dom._Translate import GetGenericsFromChainedNodes, GetPortsFromChainedNodes, GetName from pyGHDL.dom._Translate import GetDeclaredItemsFromChainedNodes, GetConcurrentStatementsFromChainedNodes +from pyGHDL.dom.Names import SimpleName from pyGHDL.dom.Symbol import EntitySymbol, ContextReferenceSymbol, LibraryReferenceSymbol, PackageSymbol, PackageMemberReferenceSymbol @@ -245,11 +246,11 @@ class PackageBody(VHDLModel_PackageBody, DOMMixin): @classmethod def parse(cls, packageBodyNode: Iir, contextItems: Iterable[VHDLModel_ContextUnion]): - packageName = GetName(packageBodyNode) - packageSymbol = PackageSymbol(packageBodyNode, packageName) + packageIdentifier = GetNameOfNode(packageBodyNode) + packageSymbol = PackageSymbol(packageBodyNode, SimpleName(packageBodyNode, packageIdentifier)) documentation = GetDocumentationOfNode(packageBodyNode) declaredItems = GetDeclaredItemsFromChainedNodes( - nodes.Get_Declaration_Chain(packageBodyNode), "package", packageName + nodes.Get_Declaration_Chain(packageBodyNode), "package", packageIdentifier ) # FIXME: read use clauses @@ -309,7 +310,7 @@ class Context(VHDLModel_Context, DOMMixin): kind = GetIirKindOfNode(item) if kind is nodes.Iir_Kind.Library_Clause: libraryIdentifier = GetNameOfNode(item) - names.append(LibraryReferenceSymbol(item, libraryIdentifier)) + names.append(LibraryReferenceSymbol(item, SimpleName(item, libraryIdentifier))) if nodes.Get_Has_Identifier_List(item): continue diff --git a/pyGHDL/dom/NonStandard.py b/pyGHDL/dom/NonStandard.py index 31cc28480..d4e2fa1a5 100644 --- a/pyGHDL/dom/NonStandard.py +++ b/pyGHDL/dom/NonStandard.py @@ -40,6 +40,7 @@ import time from pathlib import Path from typing import Any +from pyGHDL.dom.Names import SimpleName from pyTooling.Decorators import export, InheritDocString from pyVHDLModel import VHDLVersion @@ -208,7 +209,7 @@ class Document(VHDLModel_Document): itemKind = GetIirKindOfNode(item) if itemKind is nodes.Iir_Kind.Library_Clause: libraryIdentifier = GetNameOfNode(item) - contextNames.append(LibraryReferenceSymbol(item, libraryIdentifier)) + contextNames.append(LibraryReferenceSymbol(item, SimpleName(item, libraryIdentifier))) if nodes.Get_Has_Identifier_List(item): continue diff --git a/pyGHDL/dom/Sequential.py b/pyGHDL/dom/Sequential.py index f289ae969..e76cdd440 100644 --- a/pyGHDL/dom/Sequential.py +++ b/pyGHDL/dom/Sequential.py @@ -335,7 +335,7 @@ class ForLoopStatement(VHDLModel_ForLoopStatement, DOMMixin): @classmethod def parse(cls, loopNode: Iir, label: str) -> "ForLoopStatement": - from pyGHDL.dom._Utils import GetIirKindOfNode + from pyGHDL.dom._Utils import GetNameOfNode, GetIirKindOfNode from pyGHDL.dom._Translate import ( GetSequentialStatementsFromChainedNodes, GetRangeFromNode, @@ -343,7 +343,7 @@ class ForLoopStatement(VHDLModel_ForLoopStatement, DOMMixin): ) spec = nodes.Get_Parameter_Specification(loopNode) - loopIndex = GetName(spec) + loopIndex = GetNameOfNode(spec) discreteRange = nodes.Get_Discrete_Range(spec) rangeKind = GetIirKindOfNode(discreteRange) diff --git a/pyGHDL/dom/Subprogram.py b/pyGHDL/dom/Subprogram.py index 17661b8b2..6bb13dcd9 100644 --- a/pyGHDL/dom/Subprogram.py +++ b/pyGHDL/dom/Subprogram.py @@ -67,6 +67,7 @@ class Function(VHDLModel_Function, DOMMixin): @classmethod def parse(cls, functionNode: Iir) -> "Function": from pyGHDL.dom._Translate import ( + GetName, GetGenericsFromChainedNodes, GetParameterFromChainedNodes, ) @@ -78,7 +79,7 @@ class Function(VHDLModel_Function, DOMMixin): parameters = GetParameterFromChainedNodes(nodes.Get_Interface_Declaration_Chain(functionNode)) returnType = nodes.Get_Return_Type_Mark(functionNode) - returnTypeName = GetNameOfNode(returnType) + returnTypeName = GetName(returnType) returnTypeSymbol = SimpleSubtypeSymbol(returnType, returnTypeName) return cls(functionNode, functionName, returnTypeSymbol, generics, parameters, documentation) diff --git a/pyGHDL/dom/Symbol.py b/pyGHDL/dom/Symbol.py index fe3f3bbe0..40e9fe55e 100644 --- a/pyGHDL/dom/Symbol.py +++ b/pyGHDL/dom/Symbol.py @@ -144,16 +144,15 @@ class PackageSymbol(VHDLModel_PackageSymbol, DOMMixin): @export class SimpleSubtypeSymbol(VHDLModel_SimpleSubtypeSymbol, DOMMixin): - def __init__(self, node: Iir, subtypeName: str): - if isinstance(subtypeName, (List, Iterator)): - subtypeName = ".".join(subtypeName) - + @InheritDocString(VHDLModel_SimpleSubtypeSymbol) + def __init__(self, node: Iir, subtypeName: Name): super().__init__(subtypeName) DOMMixin.__init__(self, node) @export class ConstrainedScalarSubtypeSymbol(VHDLModel_ConstrainedScalarSubtypeSymbol, DOMMixin): + @InheritDocString(VHDLModel_ConstrainedScalarSubtypeSymbol) def __init__(self, node: Iir, subtypeName: Name, rng: Range = None): super().__init__(subtypeName) # , rng) # XXX: hacked DOMMixin.__init__(self, node) @@ -165,6 +164,7 @@ class ConstrainedScalarSubtypeSymbol(VHDLModel_ConstrainedScalarSubtypeSymbol, D @export class ConstrainedCompositeSubtypeSymbol(VHDLModel_ConstrainedCompositeSubtypeSymbol, DOMMixin): + @InheritDocString(VHDLModel_ConstrainedCompositeSubtypeSymbol) def __init__(self, node: Iir, subtypeName: Name, constraints: List = None): super().__init__(subtypeName) # , constraints) # XXX: hacked DOMMixin.__init__(self, node) @@ -176,6 +176,7 @@ class ConstrainedCompositeSubtypeSymbol(VHDLModel_ConstrainedCompositeSubtypeSym @export class SimpleObjectOrFunctionCallSymbol(VHDLModel_SimpleObjectOrFunctionCallSymbol, DOMMixin): + @InheritDocString(VHDLModel_SimpleObjectOrFunctionCallSymbol) def __init__(self, node: Iir, name: Name): super().__init__(name) DOMMixin.__init__(self, node) @@ -191,6 +192,7 @@ class SimpleObjectOrFunctionCallSymbol(VHDLModel_SimpleObjectOrFunctionCallSymbo @export class IndexedObjectOrFunctionCallSymbol(VHDLModel_IndexedObjectOrFunctionCallSymbol, DOMMixin): + @InheritDocString(VHDLModel_IndexedObjectOrFunctionCallSymbol) def __init__(self, node: Iir, name: Name): super().__init__(name) DOMMixin.__init__(self, node) diff --git a/pyGHDL/dom/Type.py b/pyGHDL/dom/Type.py index 7df1ad7a1..98dab3af0 100644 --- a/pyGHDL/dom/Type.py +++ b/pyGHDL/dom/Type.py @@ -32,6 +32,7 @@ # ============================================================================ from typing import List, Union, Iterator, Tuple, Iterable +from pyGHDL.dom.Names import SimpleName from pyTooling.Decorators import export from pyVHDLModel.Name import Name @@ -313,7 +314,7 @@ class FileType(VHDLModel_FileType, DOMMixin): designatedSubtypeMark = nodes.Get_File_Type_Mark(typeDefinitionNode) designatedSubtypeName = GetNameOfNode(designatedSubtypeMark) - designatedSubtype = SimpleSubtypeSymbol(typeDefinitionNode, designatedSubtypeName) + designatedSubtype = SimpleSubtypeSymbol(typeDefinitionNode, SimpleName(designatedSubtypeName)) return cls(typeDefinitionNode, typeName, designatedSubtype) diff --git a/pyGHDL/dom/_Translate.py b/pyGHDL/dom/_Translate.py index 8ab6283b2..97c33cf7c 100644 --- a/pyGHDL/dom/_Translate.py +++ b/pyGHDL/dom/_Translate.py @@ -322,7 +322,7 @@ def GetSubtypeIndicationFromIndicationNode(subtypeIndicationNode: Iir, entity: s @export def GetSimpleTypeFromNode(subtypeIndicationNode: Iir) -> SimpleSubtypeSymbol: subtypeName = GetName(subtypeIndicationNode) - return SimpleSubtypeSymbol(subtypeIndicationNode, str(subtypeName)) # XXX: hacked + return SimpleSubtypeSymbol(subtypeIndicationNode, subtypeName) @export @@ -340,7 +340,7 @@ def GetScalarConstrainedSubtypeFromNode( r = GetRangeFromNode(rangeConstraint) # todo: Get actual range from AttributeName node? - return ConstrainedScalarSubtypeSymbol(subtypeIndicationNode, str(simpleTypeMark), r) # XXX: hacked + return ConstrainedScalarSubtypeSymbol(subtypeIndicationNode, simpleTypeMark, r) @export -- cgit v1.2.3 From 9d920a551e9108d9ddc99c87e8f2f5f8744ff418 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sat, 15 Apr 2023 18:38:14 +0200 Subject: Fixes due to errors reported by unit tests. --- pyGHDL/dom/Attribute.py | 2 +- pyGHDL/dom/Expression.py | 4 ++-- pyGHDL/dom/Type.py | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/pyGHDL/dom/Attribute.py b/pyGHDL/dom/Attribute.py index 08295817d..46ea109aa 100644 --- a/pyGHDL/dom/Attribute.py +++ b/pyGHDL/dom/Attribute.py @@ -63,7 +63,7 @@ class Attribute(VHDLModel_Attribute, DOMMixin): subtypeMark = nodes.Get_Type_Mark(attributeNode) subtypeName = GetNameOfNode(subtypeMark) - subtype = SimpleSubtypeSymbol(subtypeMark, SimpleName(subtypeName)) + subtype = SimpleSubtypeSymbol(subtypeMark, SimpleName(subtypeMark, subtypeName)) return cls(attributeNode, name, subtype, documentation) diff --git a/pyGHDL/dom/Expression.py b/pyGHDL/dom/Expression.py index 0d8dbfba7..532a1c9ed 100644 --- a/pyGHDL/dom/Expression.py +++ b/pyGHDL/dom/Expression.py @@ -439,9 +439,9 @@ class QualifiedExpression(VHDLModel_QualifiedExpression, DOMMixin): @classmethod def parse(cls, node: Iir) -> "QualifiedExpression": - from pyGHDL.dom._Translate import GetExpressionFromNode, GetNameOfNode + from pyGHDL.dom._Translate import GetExpressionFromNode, GetName - typeMarkName = GetNameOfNode(nodes.Get_Type_Mark(node)) + typeMarkName = GetName(nodes.Get_Type_Mark(node)) subtype = SimpleSubtypeSymbol(node, typeMarkName) operand = GetExpressionFromNode(nodes.Get_Expression(node)) return cls(node, subtype, operand) diff --git a/pyGHDL/dom/Type.py b/pyGHDL/dom/Type.py index 98dab3af0..b0102217c 100644 --- a/pyGHDL/dom/Type.py +++ b/pyGHDL/dom/Type.py @@ -314,7 +314,7 @@ class FileType(VHDLModel_FileType, DOMMixin): designatedSubtypeMark = nodes.Get_File_Type_Mark(typeDefinitionNode) designatedSubtypeName = GetNameOfNode(designatedSubtypeMark) - designatedSubtype = SimpleSubtypeSymbol(typeDefinitionNode, SimpleName(designatedSubtypeName)) + designatedSubtype = SimpleSubtypeSymbol(typeDefinitionNode, SimpleName(designatedSubtypeMark, designatedSubtypeName)) return cls(typeDefinitionNode, typeName, designatedSubtype) -- cgit v1.2.3 From 636bdef4116fc635b2f4be04db7ab06543085121 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sat, 15 Apr 2023 19:10:33 +0200 Subject: Formatting by black. --- pyGHDL/dom/Concurrent.py | 6 +++++- pyGHDL/dom/DesignUnit.py | 10 ++++++++-- pyGHDL/dom/Type.py | 4 +++- 3 files changed, 16 insertions(+), 4 deletions(-) diff --git a/pyGHDL/dom/Concurrent.py b/pyGHDL/dom/Concurrent.py index 303b6b96b..ea46b4995 100644 --- a/pyGHDL/dom/Concurrent.py +++ b/pyGHDL/dom/Concurrent.py @@ -224,7 +224,11 @@ class ProcessStatement(VHDLModel_ProcessStatement, DOMMixin): @classmethod def parse(cls, processNode: Iir, label: str, hasSensitivityList: bool) -> "ProcessStatement": - from pyGHDL.dom._Translate import GetName, GetDeclaredItemsFromChainedNodes, GetSequentialStatementsFromChainedNodes + from pyGHDL.dom._Translate import ( + GetName, + GetDeclaredItemsFromChainedNodes, + GetSequentialStatementsFromChainedNodes, + ) sensitivityList = None if hasSensitivityList: diff --git a/pyGHDL/dom/DesignUnit.py b/pyGHDL/dom/DesignUnit.py index 9779a7ea0..cfaa7d55f 100644 --- a/pyGHDL/dom/DesignUnit.py +++ b/pyGHDL/dom/DesignUnit.py @@ -66,8 +66,14 @@ from pyGHDL.dom import DOMMixin, Position, DOMException from pyGHDL.dom._Utils import GetNameOfNode, GetDocumentationOfNode, GetPackageMemberSymbol from pyGHDL.dom._Translate import GetGenericsFromChainedNodes, GetPortsFromChainedNodes, GetName from pyGHDL.dom._Translate import GetDeclaredItemsFromChainedNodes, GetConcurrentStatementsFromChainedNodes -from pyGHDL.dom.Names import SimpleName -from pyGHDL.dom.Symbol import EntitySymbol, ContextReferenceSymbol, LibraryReferenceSymbol, PackageSymbol, PackageMemberReferenceSymbol +from pyGHDL.dom.Names import SimpleName +from pyGHDL.dom.Symbol import ( + EntitySymbol, + ContextReferenceSymbol, + LibraryReferenceSymbol, + PackageSymbol, + PackageMemberReferenceSymbol, +) @export diff --git a/pyGHDL/dom/Type.py b/pyGHDL/dom/Type.py index b0102217c..0ec7a9d9a 100644 --- a/pyGHDL/dom/Type.py +++ b/pyGHDL/dom/Type.py @@ -314,7 +314,9 @@ class FileType(VHDLModel_FileType, DOMMixin): designatedSubtypeMark = nodes.Get_File_Type_Mark(typeDefinitionNode) designatedSubtypeName = GetNameOfNode(designatedSubtypeMark) - designatedSubtype = SimpleSubtypeSymbol(typeDefinitionNode, SimpleName(designatedSubtypeMark, designatedSubtypeName)) + designatedSubtype = SimpleSubtypeSymbol( + typeDefinitionNode, SimpleName(designatedSubtypeMark, designatedSubtypeName) + ) return cls(typeDefinitionNode, typeName, designatedSubtype) -- cgit v1.2.3 From e58078203afbdde0fb41c5a3ec43c80312cbbd8b Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sat, 15 Apr 2023 23:55:17 +0200 Subject: Removed Get**Symbol functions. --- pyGHDL/dom/DesignUnit.py | 2 +- pyGHDL/dom/Symbol.py | 1 - pyGHDL/dom/_Utils.py | 58 +----------------------------------------------- 3 files changed, 2 insertions(+), 59 deletions(-) diff --git a/pyGHDL/dom/DesignUnit.py b/pyGHDL/dom/DesignUnit.py index cfaa7d55f..48ae24b6f 100644 --- a/pyGHDL/dom/DesignUnit.py +++ b/pyGHDL/dom/DesignUnit.py @@ -63,7 +63,7 @@ from pyGHDL.libghdl import utils from pyGHDL.libghdl._types import Iir from pyGHDL.libghdl.vhdl import nodes from pyGHDL.dom import DOMMixin, Position, DOMException -from pyGHDL.dom._Utils import GetNameOfNode, GetDocumentationOfNode, GetPackageMemberSymbol +from pyGHDL.dom._Utils import GetNameOfNode, GetDocumentationOfNode from pyGHDL.dom._Translate import GetGenericsFromChainedNodes, GetPortsFromChainedNodes, GetName from pyGHDL.dom._Translate import GetDeclaredItemsFromChainedNodes, GetConcurrentStatementsFromChainedNodes from pyGHDL.dom.Names import SimpleName diff --git a/pyGHDL/dom/Symbol.py b/pyGHDL/dom/Symbol.py index 40e9fe55e..456c96847 100644 --- a/pyGHDL/dom/Symbol.py +++ b/pyGHDL/dom/Symbol.py @@ -39,7 +39,6 @@ from pyVHDLModel.Base import ExpressionUnion from pyVHDLModel.Symbol import LibraryReferenceSymbol as VHDLModel_LibraryReferenceSymbol from pyVHDLModel.Symbol import PackageReferenceSymbol as VHDLModel_PackageReferenceSymbol from pyVHDLModel.Symbol import PackageMembersReferenceSymbol as VHDLModel_PackageMembersReferenceSymbol -from pyVHDLModel.Symbol import AllPackageMembersReferenceSymbol as VHDLModel_AllPackageMembersReferenceSymbol from pyVHDLModel.Symbol import ContextReferenceSymbol as VHDLModel_ContextReferenceSymbol from pyVHDLModel.Symbol import EntitySymbol as VHDLModel_EntitySymbol from pyVHDLModel.Symbol import ArchitectureSymbol as VHDLModel_ArchitectureSymbol diff --git a/pyGHDL/dom/_Utils.py b/pyGHDL/dom/_Utils.py index 5a9c1c135..f8358cb2c 100644 --- a/pyGHDL/dom/_Utils.py +++ b/pyGHDL/dom/_Utils.py @@ -30,20 +30,15 @@ # # SPDX-License-Identifier: GPL-2.0-or-later # ============================================================================ -from typing import Union - from pyTooling.Decorators import export from pyVHDLModel.Base import Mode -from pyVHDLModel.Name import Name -from pyVHDLModel.Symbol import PackageMembersReferenceSymbol, AllPackageMembersReferenceSymbol from pyGHDL.libghdl import LibGHDLException, name_table, errorout_memory, files_map, file_comments from pyGHDL.libghdl._types import Iir from pyGHDL.libghdl.vhdl import nodes, utils from pyGHDL.libghdl.vhdl.nodes import Null_Iir -from pyGHDL.dom import DOMException, Position -from pyGHDL.dom.Names import SelectedName, AllName, SimpleName +from pyGHDL.dom import DOMException __MODE_TRANSLATION = { nodes.Iir_Mode.In_Mode: Mode.In, @@ -139,54 +134,3 @@ def GetModeOfNode(node: Iir) -> Mode: return __MODE_TRANSLATION[nodes.Get_Mode(node)] except KeyError as ex: raise DOMException(f"Unknown mode '{ex.args[0]}'.") from ex - - -def GetLibrarySymbol(node: Iir) -> LibraryReferenceSymbol: - kind = GetIirKindOfNode(node) - if kind == nodes.Iir_Kind.Simple_Name: - name = GetNameOfNode(node) - return LibraryReferenceSymbol(node, name) - else: - raise DOMException(f"{kind} at {Position.parse(node)}") - - -def GetPackageSymbol(node: Iir) -> PackageReferenceSymbol: - kind = GetIirKindOfNode(node) - name = GetNameOfNode(node) - if kind == nodes.Iir_Kind.Selected_Name: - prefixName = GetLibrarySymbol(nodes.Get_Prefix(node)) - return PackageReferenceSymbol(node, name, prefixName) - elif kind == nodes.Iir_Kind.Simple_Name: - return PackageReferenceSymbol(node, name, None) - else: - raise DOMException(f"{kind.name} at {Position.parse(node)}") - - -def GetPackageMemberSymbol( - node: Iir, -) -> Union[PackageMembersReferenceSymbol, AllPackageMembersReferenceSymbol]: - from pyGHDL.dom._Translate import GetName - - name = GetName(node) - if isinstance(name, AllName): - return AllPackageMembersReferenceSymbol(name) - else: - raise DOMException(f"{kind.name} at {Position.parse(node)}") - - -def GetComponentInstantiationSymbol(node: Iir) -> ComponentInstantiationSymbol: - kind = GetIirKindOfNode(node) - if kind == nodes.Iir_Kind.Simple_Name: - name = GetNameOfNode(node) - return ComponentInstantiationSymbol(node, name) - else: - raise DOMException(f"{kind.name} at {Position.parse(node)}") - - -def GetConfigurationInstantiationSymbol(node: Iir) -> ConfigurationInstantiationSymbol: - kind = GetIirKindOfNode(node) - if kind == nodes.Iir_Kind.Simple_Name: - name = GetNameOfNode(node) - return ConfigurationInstantiationSymbol(node, name) - else: - raise DOMException(f"{kind.name} at {Position.parse(node)}") -- cgit v1.2.3 From c3d8e45a45b758bc9dcc38390408e39e01c7be4c Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sun, 16 Apr 2023 07:23:28 +0200 Subject: Bumped dependencies. --- pyGHDL/cli/requirements.txt | 1 - pyGHDL/dom/requirements.txt | 2 +- testsuite/requirements.txt | 2 +- 3 files changed, 2 insertions(+), 3 deletions(-) diff --git a/pyGHDL/cli/requirements.txt b/pyGHDL/cli/requirements.txt index a2fdd82b3..f12f728ea 100644 --- a/pyGHDL/cli/requirements.txt +++ b/pyGHDL/cli/requirements.txt @@ -1,5 +1,4 @@ -r ../dom/requirements.txt pyTooling>=4.0.1, <5.0 -pyTooling.TerminalUI>=1.5.9 pyAttributes>=2.3.2 diff --git a/pyGHDL/dom/requirements.txt b/pyGHDL/dom/requirements.txt index dcded04a0..39ed6ca73 100644 --- a/pyGHDL/dom/requirements.txt +++ b/pyGHDL/dom/requirements.txt @@ -1,4 +1,4 @@ -r ../libghdl/requirements.txt -pyVHDLModel==0.24.1 +pyVHDLModel==0.25.0 #https://github.com/VHDL/pyVHDLModel/archive/dev.zip#pyVHDLModel diff --git a/testsuite/requirements.txt b/testsuite/requirements.txt index 576b49bc0..3b2b87b7c 100644 --- a/testsuite/requirements.txt +++ b/testsuite/requirements.txt @@ -4,4 +4,4 @@ pytest>=7.3.0 pytest-cov>=2.10.1 # Coverage collection -Coverage>=5.3 +Coverage>=7.2 -- cgit v1.2.3 From a211cdcf7d5eb5f058d2e38c93092f4548283451 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sun, 16 Apr 2023 11:17:29 +0200 Subject: Fixed expression. --- testsuite/pyunit/dom/Expressions.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/testsuite/pyunit/dom/Expressions.py b/testsuite/pyunit/dom/Expressions.py index fe9bf22eb..290216156 100644 --- a/testsuite/pyunit/dom/Expressions.py +++ b/testsuite/pyunit/dom/Expressions.py @@ -34,7 +34,7 @@ import ctypes from inspect import currentframe from pathlib import Path from textwrap import dedent -from typing import TypeVar, Dict +from typing import TypeVar, Dict, cast from unittest import TestCase @@ -89,7 +89,7 @@ class Expressions(TestCase): ) # Define test data - constantDeclartion = "constant c0 : boolean := not true;" + constantDeclartion = "constant c0 : boolean := not True;" # Parse in-memory default: Expression = self.parse(filename, constantDeclartion) @@ -97,7 +97,7 @@ class Expressions(TestCase): # Start checks self.assertIsInstance(default, InverseExpression) self.assertIsInstance(default.Operand, SimpleObjectOrFunctionCallSymbol) - self.assertEqual("true", str(default.Operand)) # .SymbolName)) # XXX: hacked + self.assertEqual("True", cast(SimpleObjectOrFunctionCallSymbol, default.Operand).Name.Identifier) # def test_AbsExpression(self): # filename: Path = self._root / "{className}_{funcName}.vhdl".format( -- cgit v1.2.3 From 61bb37c757e5167b617823d6b100edf54de154d6 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sun, 16 Apr 2023 19:43:35 +0200 Subject: Fixed last testcase. --- pyGHDL/dom/DesignUnit.py | 11 ++++++++--- pyGHDL/dom/Symbol.py | 15 ++++++++++++--- pyGHDL/dom/formatting/GraphML.py | 2 +- testsuite/pyunit/dom/Expressions.py | 4 +--- 4 files changed, 22 insertions(+), 10 deletions(-) diff --git a/pyGHDL/dom/DesignUnit.py b/pyGHDL/dom/DesignUnit.py index 48ae24b6f..edca0789e 100644 --- a/pyGHDL/dom/DesignUnit.py +++ b/pyGHDL/dom/DesignUnit.py @@ -66,13 +66,14 @@ from pyGHDL.dom import DOMMixin, Position, DOMException from pyGHDL.dom._Utils import GetNameOfNode, GetDocumentationOfNode from pyGHDL.dom._Translate import GetGenericsFromChainedNodes, GetPortsFromChainedNodes, GetName from pyGHDL.dom._Translate import GetDeclaredItemsFromChainedNodes, GetConcurrentStatementsFromChainedNodes -from pyGHDL.dom.Names import SimpleName +from pyGHDL.dom.Names import SimpleName, AllName from pyGHDL.dom.Symbol import ( EntitySymbol, ContextReferenceSymbol, LibraryReferenceSymbol, PackageSymbol, PackageMemberReferenceSymbol, + AllPackageMembersReferenceSymbol ) @@ -92,10 +93,14 @@ class UseClause(VHDLModel_UseClause, DOMMixin): @classmethod def parse(cls, useNode: Iir): nameNode = nodes.Get_Selected_Name(useNode) - uses = [PackageMemberReferenceSymbol(nameNode, GetName(nameNode))] + name = GetName(nameNode) + symbolType = AllPackageMembersReferenceSymbol if isinstance(name, AllName) else PackageMemberReferenceSymbol + uses = [symbolType(nameNode, name)] for use in utils.chain_iter(nodes.Get_Use_Clause_Chain(useNode)): nameNode = nodes.Get_Selected_Name(use) - uses.append(PackageMemberReferenceSymbol(nameNode, GetName(nameNode))) + name = GetName(nameNode) + symbolType = AllPackageMembersReferenceSymbol if isinstance(name, AllName) else PackageMemberReferenceSymbol + uses.append(symbolType(nameNode, name)) return cls(useNode, uses) diff --git a/pyGHDL/dom/Symbol.py b/pyGHDL/dom/Symbol.py index 456c96847..05057793d 100644 --- a/pyGHDL/dom/Symbol.py +++ b/pyGHDL/dom/Symbol.py @@ -38,7 +38,8 @@ from pyVHDLModel import Name from pyVHDLModel.Base import ExpressionUnion from pyVHDLModel.Symbol import LibraryReferenceSymbol as VHDLModel_LibraryReferenceSymbol from pyVHDLModel.Symbol import PackageReferenceSymbol as VHDLModel_PackageReferenceSymbol -from pyVHDLModel.Symbol import PackageMembersReferenceSymbol as VHDLModel_PackageMembersReferenceSymbol +from pyVHDLModel.Symbol import PackageMemberReferenceSymbol as VHDLModel_PackageMemberReferenceSymbol +from pyVHDLModel.Symbol import AllPackageMembersReferenceSymbol as VHDLModel_AllPackageMembersReferenceSymbol from pyVHDLModel.Symbol import ContextReferenceSymbol as VHDLModel_ContextReferenceSymbol from pyVHDLModel.Symbol import EntitySymbol as VHDLModel_EntitySymbol from pyVHDLModel.Symbol import ArchitectureSymbol as VHDLModel_ArchitectureSymbol @@ -82,8 +83,16 @@ class ContextReferenceSymbol(VHDLModel_ContextReferenceSymbol, DOMMixin): @export -class PackageMemberReferenceSymbol(VHDLModel_PackageMembersReferenceSymbol, DOMMixin): - @InheritDocString(VHDLModel_PackageMembersReferenceSymbol) +class PackageMemberReferenceSymbol(VHDLModel_PackageMemberReferenceSymbol, DOMMixin): + @InheritDocString(VHDLModel_PackageMemberReferenceSymbol) + def __init__(self, identifierNode: Iir, name: Name): + super().__init__(name) + DOMMixin.__init__(self, identifierNode) + + +@export +class AllPackageMembersReferenceSymbol(VHDLModel_AllPackageMembersReferenceSymbol, DOMMixin): + @InheritDocString(VHDLModel_AllPackageMembersReferenceSymbol) def __init__(self, identifierNode: Iir, name: Name): super().__init__(name) DOMMixin.__init__(self, identifierNode) diff --git a/pyGHDL/dom/formatting/GraphML.py b/pyGHDL/dom/formatting/GraphML.py index 7f72d54b5..0ad31e33f 100644 --- a/pyGHDL/dom/formatting/GraphML.py +++ b/pyGHDL/dom/formatting/GraphML.py @@ -91,7 +91,7 @@ class DependencyGraphFormatter: for vertex in vertices: if vertex["kind"] is DependencyGraphVertexKind.Architecture: - value = f"{vertex.Value.Entity.Identifier}({vertex.Value.Identifier})" + value = f"{vertex.Value.Entity.Name.Identifier}({vertex.Value.Identifier})" elif vertex["kind"] is DependencyGraphVertexKind.Document: value = f"{vertex.ID}" else: diff --git a/testsuite/pyunit/dom/Expressions.py b/testsuite/pyunit/dom/Expressions.py index 290216156..24235e1e1 100644 --- a/testsuite/pyunit/dom/Expressions.py +++ b/testsuite/pyunit/dom/Expressions.py @@ -84,9 +84,7 @@ class Expressions(TestCase): return default def test_NotExpression(self): - filename: Path = self._root / "{className}_{funcName}.vhdl".format( - className=self.__class__.__name__, funcName= currentframe().f_code.co_name[5:] - ) + filename: Path = self._root / f"{self.__class__.__name__}_{currentframe().f_code.co_name[5:]}.vhdl" # Define test data constantDeclartion = "constant c0 : boolean := not True;" -- cgit v1.2.3 From 989ec4ce0d43b90a5ada0a582c5b1ec6e610cb06 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sun, 16 Apr 2023 20:03:06 +0200 Subject: Bumped dependencies. --- pyGHDL/dom/DesignUnit.py | 2 +- pyGHDL/dom/requirements.txt | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/pyGHDL/dom/DesignUnit.py b/pyGHDL/dom/DesignUnit.py index edca0789e..9e9df15d0 100644 --- a/pyGHDL/dom/DesignUnit.py +++ b/pyGHDL/dom/DesignUnit.py @@ -73,7 +73,7 @@ from pyGHDL.dom.Symbol import ( LibraryReferenceSymbol, PackageSymbol, PackageMemberReferenceSymbol, - AllPackageMembersReferenceSymbol + AllPackageMembersReferenceSymbol, ) diff --git a/pyGHDL/dom/requirements.txt b/pyGHDL/dom/requirements.txt index 39ed6ca73..412092e43 100644 --- a/pyGHDL/dom/requirements.txt +++ b/pyGHDL/dom/requirements.txt @@ -1,4 +1,4 @@ -r ../libghdl/requirements.txt -pyVHDLModel==0.25.0 +pyVHDLModel==0.25.1 #https://github.com/VHDL/pyVHDLModel/archive/dev.zip#pyVHDLModel -- cgit v1.2.3