From cb4c462d9868b8fb93ef8cc79aa5a016a923ace7 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Mon, 30 Mar 2020 07:03:35 +0200
Subject: testsuite/synth: add tests for #1177

---
 testsuite/synth/issue1177/issue1.vhdl  | 15 +++++++++++++++
 testsuite/synth/issue1177/issue2.vhdl  | 15 +++++++++++++++
 testsuite/synth/issue1177/testsuite.sh | 10 ++++++++++
 3 files changed, 40 insertions(+)
 create mode 100644 testsuite/synth/issue1177/issue1.vhdl
 create mode 100644 testsuite/synth/issue1177/issue2.vhdl
 create mode 100755 testsuite/synth/issue1177/testsuite.sh

diff --git a/testsuite/synth/issue1177/issue1.vhdl b/testsuite/synth/issue1177/issue1.vhdl
new file mode 100644
index 000000000..5d18a0f57
--- /dev/null
+++ b/testsuite/synth/issue1177/issue1.vhdl
@@ -0,0 +1,15 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity issue1 is
+    port (foo : in  std_logic;
+          bar : out boolean);
+end issue1;
+
+architecture behav of issue1 is
+begin
+
+    bar <= (?? foo);
+
+end architecture;
+
diff --git a/testsuite/synth/issue1177/issue2.vhdl b/testsuite/synth/issue1177/issue2.vhdl
new file mode 100644
index 000000000..efe94ddd9
--- /dev/null
+++ b/testsuite/synth/issue1177/issue2.vhdl
@@ -0,0 +1,15 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity issue2 is
+    port (foo : in  std_logic;
+          bar : out boolean);
+end issue2;
+
+architecture behav of issue2 is
+begin
+
+  --bar <= true when (?? foo) else false; -- works
+    bar <= true when false xor (?? foo) else false;
+
+end architecture;
diff --git a/testsuite/synth/issue1177/testsuite.sh b/testsuite/synth/issue1177/testsuite.sh
new file mode 100755
index 000000000..8cbfe93fd
--- /dev/null
+++ b/testsuite/synth/issue1177/testsuite.sh
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+synth_analyze issue1
+synth_analyze issue2
+
+clean
+echo "Test successful"
-- 
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