From bc31638a6c7ab04bc5e71941dd69ff13e9d19ec7 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Fri, 15 May 2020 07:36:29 +0200
Subject: testsuite/synth: add a test for #1311

---
 testsuite/synth/issue1311/issue.vhdl    | 12 ++++++++++++
 testsuite/synth/issue1311/tb_issue.vhdl | 19 +++++++++++++++++++
 testsuite/synth/issue1311/testsuite.sh  |  7 +++++++
 3 files changed, 38 insertions(+)
 create mode 100644 testsuite/synth/issue1311/issue.vhdl
 create mode 100644 testsuite/synth/issue1311/tb_issue.vhdl
 create mode 100755 testsuite/synth/issue1311/testsuite.sh

diff --git a/testsuite/synth/issue1311/issue.vhdl b/testsuite/synth/issue1311/issue.vhdl
new file mode 100644
index 000000000..41575a46b
--- /dev/null
+++ b/testsuite/synth/issue1311/issue.vhdl
@@ -0,0 +1,12 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity issue is
+    port (foo : out boolean);
+end issue;
+
+architecture beh of issue is
+    signal bar : std_logic_vector (7 downto 0);
+begin
+    foo <= bar (0 downto 1) = bar (1 downto 2);
+end architecture beh;
diff --git a/testsuite/synth/issue1311/tb_issue.vhdl b/testsuite/synth/issue1311/tb_issue.vhdl
new file mode 100644
index 000000000..80e07dba5
--- /dev/null
+++ b/testsuite/synth/issue1311/tb_issue.vhdl
@@ -0,0 +1,19 @@
+entity tb_issue is
+end tb_issue;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_issue is
+  signal a : boolean;
+begin
+  dut: entity work.issue
+    port map (a);
+
+  process
+  begin
+    wait for 1 ns;
+    assert a severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1311/testsuite.sh b/testsuite/synth/issue1311/testsuite.sh
new file mode 100755
index 000000000..d580d8433
--- /dev/null
+++ b/testsuite/synth/issue1311/testsuite.sh
@@ -0,0 +1,7 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_tb issue
+
+echo "Test successful"
-- 
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