From bb357cf03c7e956db1539712fd64353b6d87872d Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Fri, 10 Jun 2022 06:36:49 +0200 Subject: vhdl: recognize ieee.math_real.sign, fix is_x recogn. --- pyGHDL/libghdl/std_names.py | 395 +++++++++++++++++----------------- pyGHDL/libghdl/vhdl/nodes.py | 4 +- src/std_names.adb | 1 + src/std_names.ads | 13 +- src/synth/synth-vhdl_eval.adb | 25 ++- src/synth/synth-vhdl_oper.adb | 4 +- src/vhdl/vhdl-ieee-math_real.adb | 2 + src/vhdl/vhdl-ieee-std_logic_1164.adb | 20 +- src/vhdl/vhdl-nodes.ads | 4 +- 9 files changed, 251 insertions(+), 217 deletions(-) diff --git a/pyGHDL/libghdl/std_names.py b/pyGHDL/libghdl/std_names.py index 961a0d247..5efe42fb5 100644 --- a/pyGHDL/libghdl/std_names.py +++ b/pyGHDL/libghdl/std_names.py @@ -636,200 +636,201 @@ class Name: Sin = 841 Cos = 842 Arctan = 843 - Shl = 844 - Shr = 845 - Ext = 846 - Sxt = 847 - Find_Leftmost = 848 - Find_Rightmost = 849 - Last_Ieee_Name = 849 - First_Synthesis = 850 - Allconst = 850 - Allseq = 851 - Anyconst = 852 - Anyseq = 853 - Gclk = 854 - Loc = 855 - Keep = 856 - Syn_Black_Box = 857 - Last_Synthesis = 857 - First_Directive = 858 - Define = 858 - Endif = 859 - Ifdef = 860 - Ifndef = 861 - Include = 862 - Timescale = 863 - Undef = 864 - Protect = 865 - Begin_Protected = 866 - End_Protected = 867 - Key_Block = 868 - Data_Block = 869 - Line = 870 - Celldefine = 871 - Endcelldefine = 872 - Default_Nettype = 873 - Resetall = 874 - Last_Directive = 874 - First_Systask = 875 - Bits = 875 - D_Root = 876 - D_Unit = 877 - Last_Systask = 877 - First_SV_Method = 878 - Size = 878 - Insert = 879 - Delete = 880 - Pop_Front = 881 - Pop_Back = 882 - Push_Front = 883 - Push_Back = 884 - Name = 885 - Len = 886 - Substr = 887 - Exists = 888 - Atoi = 889 - Itoa = 890 - Find = 891 - Find_Index = 892 - Find_First = 893 - Find_First_Index = 894 - Find_Last = 895 - Find_Last_Index = 896 - Num = 897 - Randomize = 898 - Pre_Randomize = 899 - Post_Randomize = 900 - Srandom = 901 - Get_Randstate = 902 - Set_Randstate = 903 - Seed = 904 - State = 905 - Last_SV_Method = 905 - First_BSV = 906 - uAction = 906 - uActionValue = 907 - BVI = 908 - uC = 909 - uCF = 910 - uE = 911 - uSB = 912 - uSBR = 913 - Action = 914 - Endaction = 915 - Actionvalue = 916 - Endactionvalue = 917 - Ancestor = 918 - Clocked_By = 919 - Default_Clock = 920 - Default_Reset = 921 - Dependencies = 922 - Deriving = 923 - Determines = 924 - Enable = 925 - Ifc_Inout = 926 - Input_Clock = 927 - Input_Reset = 928 - Instance = 929 - Endinstance = 930 - Let = 931 - Match = 932 - Method = 933 - Endmethod = 934 - Numeric = 935 - Output_Clock = 936 - Output_Reset = 937 - Par = 938 - Endpar = 939 - Path = 940 - Provisos = 941 - Ready = 942 - Reset_By = 943 - Rule = 944 - Endrule = 945 - Rules = 946 - Endrules = 947 - Same_Family = 948 - Schedule = 949 - Seq = 950 - Endseq = 951 - Typeclass = 952 - Endtypeclass = 953 - Valueof = 954 - uValueof = 955 - Last_BSV = 955 - First_Comment = 956 - Psl = 956 - Pragma = 957 - Synthesis = 958 - Synopsys = 959 - Translate_Off = 960 - Translate_On = 961 - Translate = 962 - Synthesis_Off = 963 - Synthesis_On = 964 - Off = 965 - Full_Case = 966 - Parallel_Case = 967 - Last_Comment = 967 - First_PSL = 968 - A = 968 - Af = 969 - Ag = 970 - Ax = 971 - Abort = 972 - Assume_Guarantee = 973 - Async_Abort = 974 - Before = 975 - Clock = 976 - E = 977 - Ef = 978 - Eg = 979 - Ex = 980 - Endpoint = 981 - Eventually = 982 - Fairness = 983 - Fell = 984 - Forall = 985 - G = 986 - Inf = 987 - Never = 988 - Next_A = 989 - Next_E = 990 - Next_Event = 991 - Next_Event_A = 992 - Next_Event_E = 993 - Onehot = 994 - Onehot0 = 995 - Prev = 996 - Rose = 997 - Strong = 998 - Sync_Abort = 999 - W = 1000 - Whilenot = 1001 - Within = 1002 - X = 1003 - Last_PSL = 1003 - First_Edif = 1004 - Celltype = 1014 - View = 1015 - Viewtype = 1016 - Direction = 1017 - Contents = 1018 - Net = 1019 - Viewref = 1020 - Cellref = 1021 - Libraryref = 1022 - Portinstance = 1023 - Joined = 1024 - Portref = 1025 - Instanceref = 1026 - Design = 1027 - Designator = 1028 - Owner = 1029 - Member = 1030 - Number = 1031 - Rename = 1032 - Userdata = 1033 - Last_Edif = 1033 + Sign = 844 + Shl = 845 + Shr = 846 + Ext = 847 + Sxt = 848 + Find_Leftmost = 849 + Find_Rightmost = 850 + Last_Ieee_Name = 850 + First_Synthesis = 851 + Allconst = 851 + Allseq = 852 + Anyconst = 853 + Anyseq = 854 + Gclk = 855 + Loc = 856 + Keep = 857 + Syn_Black_Box = 858 + Last_Synthesis = 858 + First_Directive = 859 + Define = 859 + Endif = 860 + Ifdef = 861 + Ifndef = 862 + Include = 863 + Timescale = 864 + Undef = 865 + Protect = 866 + Begin_Protected = 867 + End_Protected = 868 + Key_Block = 869 + Data_Block = 870 + Line = 871 + Celldefine = 872 + Endcelldefine = 873 + Default_Nettype = 874 + Resetall = 875 + Last_Directive = 875 + First_Systask = 876 + Bits = 876 + D_Root = 877 + D_Unit = 878 + Last_Systask = 878 + First_SV_Method = 879 + Size = 879 + Insert = 880 + Delete = 881 + Pop_Front = 882 + Pop_Back = 883 + Push_Front = 884 + Push_Back = 885 + Name = 886 + Len = 887 + Substr = 888 + Exists = 889 + Atoi = 890 + Itoa = 891 + Find = 892 + Find_Index = 893 + Find_First = 894 + Find_First_Index = 895 + Find_Last = 896 + Find_Last_Index = 897 + Num = 898 + Randomize = 899 + Pre_Randomize = 900 + Post_Randomize = 901 + Srandom = 902 + Get_Randstate = 903 + Set_Randstate = 904 + Seed = 905 + State = 906 + Last_SV_Method = 906 + First_BSV = 907 + uAction = 907 + uActionValue = 908 + BVI = 909 + uC = 910 + uCF = 911 + uE = 912 + uSB = 913 + uSBR = 914 + Action = 915 + Endaction = 916 + Actionvalue = 917 + Endactionvalue = 918 + Ancestor = 919 + Clocked_By = 920 + Default_Clock = 921 + Default_Reset = 922 + Dependencies = 923 + Deriving = 924 + Determines = 925 + Enable = 926 + Ifc_Inout = 927 + Input_Clock = 928 + Input_Reset = 929 + Instance = 930 + Endinstance = 931 + Let = 932 + Match = 933 + Method = 934 + Endmethod = 935 + Numeric = 936 + Output_Clock = 937 + Output_Reset = 938 + Par = 939 + Endpar = 940 + Path = 941 + Provisos = 942 + Ready = 943 + Reset_By = 944 + Rule = 945 + Endrule = 946 + Rules = 947 + Endrules = 948 + Same_Family = 949 + Schedule = 950 + Seq = 951 + Endseq = 952 + Typeclass = 953 + Endtypeclass = 954 + Valueof = 955 + uValueof = 956 + Last_BSV = 956 + First_Comment = 957 + Psl = 957 + Pragma = 958 + Synthesis = 959 + Synopsys = 960 + Translate_Off = 961 + Translate_On = 962 + Translate = 963 + Synthesis_Off = 964 + Synthesis_On = 965 + Off = 966 + Full_Case = 967 + Parallel_Case = 968 + Last_Comment = 968 + First_PSL = 969 + A = 969 + Af = 970 + Ag = 971 + Ax = 972 + Abort = 973 + Assume_Guarantee = 974 + Async_Abort = 975 + Before = 976 + Clock = 977 + E = 978 + Ef = 979 + Eg = 980 + Ex = 981 + Endpoint = 982 + Eventually = 983 + Fairness = 984 + Fell = 985 + Forall = 986 + G = 987 + Inf = 988 + Never = 989 + Next_A = 990 + Next_E = 991 + Next_Event = 992 + Next_Event_A = 993 + Next_Event_E = 994 + Onehot = 995 + Onehot0 = 996 + Prev = 997 + Rose = 998 + Strong = 999 + Sync_Abort = 1000 + W = 1001 + Whilenot = 1002 + Within = 1003 + X = 1004 + Last_PSL = 1004 + First_Edif = 1005 + Celltype = 1015 + View = 1016 + Viewtype = 1017 + Direction = 1018 + Contents = 1019 + Net = 1020 + Viewref = 1021 + Cellref = 1022 + Libraryref = 1023 + Portinstance = 1024 + Joined = 1025 + Portref = 1026 + Instanceref = 1027 + Design = 1028 + Designator = 1029 + Owner = 1030 + Member = 1031 + Number = 1032 + Rename = 1033 + Userdata = 1034 + Last_Edif = 1034 diff --git a/pyGHDL/libghdl/vhdl/nodes.py b/pyGHDL/libghdl/vhdl/nodes.py index 4330d7fad..f0b42f3e3 100644 --- a/pyGHDL/libghdl/vhdl/nodes.py +++ b/pyGHDL/libghdl/vhdl/nodes.py @@ -1417,8 +1417,8 @@ class Iir_Predefined(IntEnum): Ieee_1164_To_UX01_Bv_Slv = 220 Ieee_1164_To_UX01_Bv_Suv = 221 Ieee_1164_To_UX01_Bit_Log = 222 - Ieee_1164_Vector_Is_X = 223 - Ieee_1164_Scalar_Is_X = 224 + Ieee_1164_Is_X_Slv = 223 + Ieee_1164_Is_X_Log = 224 Ieee_1164_Rising_Edge = 225 Ieee_1164_Falling_Edge = 226 Ieee_1164_And_Suv_Log = 227 diff --git a/src/std_names.adb b/src/std_names.adb index 649029ff7..fe0038318 100644 --- a/src/std_names.adb +++ b/src/std_names.adb @@ -678,6 +678,7 @@ package body Std_Names is Def ("sin", Name_Sin); Def ("cos", Name_Cos); Def ("arctan", Name_Arctan); + Def ("sign", Name_Sign); Def ("shl", Name_Shl); Def ("shr", Name_Shr); Def ("ext", Name_Ext); diff --git a/src/std_names.ads b/src/std_names.ads index d27494d26..7b6711c98 100644 --- a/src/std_names.ads +++ b/src/std_names.ads @@ -762,12 +762,13 @@ package Std_Names is Name_Sin : constant Name_Id := Name_First_Ieee_Name + 043; Name_Cos : constant Name_Id := Name_First_Ieee_Name + 044; Name_Arctan : constant Name_Id := Name_First_Ieee_Name + 045; - Name_Shl : constant Name_Id := Name_First_Ieee_Name + 046; - Name_Shr : constant Name_Id := Name_First_Ieee_Name + 047; - Name_Ext : constant Name_Id := Name_First_Ieee_Name + 048; - Name_Sxt : constant Name_Id := Name_First_Ieee_Name + 049; - Name_Find_Leftmost : constant Name_Id := Name_First_Ieee_Name + 050; - Name_Find_Rightmost : constant Name_Id := Name_First_Ieee_Name + 051; + Name_Sign : constant Name_Id := Name_First_Ieee_Name + 046; + Name_Shl : constant Name_Id := Name_First_Ieee_Name + 047; + Name_Shr : constant Name_Id := Name_First_Ieee_Name + 048; + Name_Ext : constant Name_Id := Name_First_Ieee_Name + 049; + Name_Sxt : constant Name_Id := Name_First_Ieee_Name + 050; + Name_Find_Leftmost : constant Name_Id := Name_First_Ieee_Name + 051; + Name_Find_Rightmost : constant Name_Id := Name_First_Ieee_Name + 052; Name_Last_Ieee_Name : constant Name_Id := Name_Find_Rightmost; Name_First_Synthesis : constant Name_Id := Name_Last_Ieee_Name + 1; diff --git a/src/synth/synth-vhdl_eval.adb b/src/synth/synth-vhdl_eval.adb index 8ffbf5c4f..96564be6a 100644 --- a/src/synth/synth-vhdl_eval.adb +++ b/src/synth/synth-vhdl_eval.adb @@ -2223,10 +2223,12 @@ package body Synth.Vhdl_Eval is | Iir_Predefined_Ieee_Numeric_Std_To_X01_Sgn => return Eval_To_X01 (Get_Memtyp (Param1), Map_X01); when Iir_Predefined_Ieee_Numeric_Std_To_X01Z_Uns - | Iir_Predefined_Ieee_Numeric_Std_To_X01Z_Sgn => + | Iir_Predefined_Ieee_Numeric_Std_To_X01Z_Sgn + | Iir_Predefined_Ieee_1164_To_X01Z_Slv => return Eval_To_X01 (Get_Memtyp (Param1), Map_X01Z); when Iir_Predefined_Ieee_Numeric_Std_To_UX01_Uns - | Iir_Predefined_Ieee_Numeric_Std_To_UX01_Sgn => + | Iir_Predefined_Ieee_Numeric_Std_To_UX01_Sgn + | Iir_Predefined_Ieee_1164_To_UX01_Slv => return Eval_To_X01 (Get_Memtyp (Param1), Map_UX01); when Iir_Predefined_Ieee_1164_To_Stdlogicvector_Bv @@ -2310,7 +2312,7 @@ package body Synth.Vhdl_Eval is return Res; end; - when Iir_Predefined_Ieee_1164_Scalar_Is_X => + when Iir_Predefined_Ieee_1164_Is_X_Log => declare B : Std_Ulogic; begin @@ -2320,7 +2322,8 @@ package body Synth.Vhdl_Eval is end; when Iir_Predefined_Ieee_Numeric_Std_Is_X_Uns - | Iir_Predefined_Ieee_Numeric_Std_Is_X_Sgn => + | Iir_Predefined_Ieee_Numeric_Std_Is_X_Sgn + | Iir_Predefined_Ieee_1164_Is_X_Slv => declare Len : constant Uns32 := Param1.Typ.Abound.Len; Res : Boolean; @@ -2392,6 +2395,20 @@ package body Synth.Vhdl_Eval is return Minmax (Get_Memtyp (Param1), Get_Memtyp (Param2), False, False); + when Iir_Predefined_Ieee_Math_Real_Sign => + declare + Val : constant Fp64 := Read_Fp64 (Param1); + Res : Fp64; + begin + if Val > 0.0 then + Res := 1.0; + elsif Val < 0.0 then + Res := -1.0; + else + Res := 0.0; + end if; + return Create_Memory_Fp64 (Res, Res_Typ); + end; when Iir_Predefined_Ieee_Math_Real_Log2 => declare function Log2 (Arg : Fp64) return Fp64; diff --git a/src/synth/synth-vhdl_oper.adb b/src/synth/synth-vhdl_oper.adb index a60e9b295..919d1f64e 100644 --- a/src/synth/synth-vhdl_oper.adb +++ b/src/synth/synth-vhdl_oper.adb @@ -1958,8 +1958,8 @@ package body Synth.Vhdl_Oper is Set_Location (Edge, Expr); return Create_Value_Net (Edge, Res_Typ); end; - when Iir_Predefined_Ieee_1164_Scalar_Is_X - | Iir_Predefined_Ieee_1164_Vector_Is_X => + when Iir_Predefined_Ieee_1164_Is_X_Log + | Iir_Predefined_Ieee_1164_Is_X_Slv => -- Always false. return Create_Value_Discrete (0, Boolean_Type); when Iir_Predefined_Ieee_1164_To_Bitvector diff --git a/src/vhdl/vhdl-ieee-math_real.adb b/src/vhdl/vhdl-ieee-math_real.adb index 1881bb322..d52b8ae85 100644 --- a/src/vhdl/vhdl-ieee-math_real.adb +++ b/src/vhdl/vhdl-ieee-math_real.adb @@ -40,6 +40,8 @@ package body Vhdl.Ieee.Math_Real is when Iir_Kind_Function_Declaration => Def := Iir_Predefined_None; case Get_Identifier (Decl) is + when Name_Sign => + Def := Iir_Predefined_Ieee_Math_Real_Sign; when Name_Mod => Def := Iir_Predefined_Ieee_Math_Real_Mod; when Name_Ceil => diff --git a/src/vhdl/vhdl-ieee-std_logic_1164.adb b/src/vhdl/vhdl-ieee-std_logic_1164.adb index ff2d95190..207d2f0c5 100644 --- a/src/vhdl/vhdl-ieee-std_logic_1164.adb +++ b/src/vhdl/vhdl-ieee-std_logic_1164.adb @@ -383,6 +383,20 @@ package body Vhdl.Ieee.Std_Logic_1164 is elsif Is_Scalar_Function (Decl) then Predefined := Iir_Predefined_Ieee_1164_To_X01_Log; end if; + when Name_To_UX01 => + if Is_Vector_Function (Decl) then + -- TODO: distinguish slv/suv. + Predefined := Iir_Predefined_Ieee_1164_To_UX01_Slv; + elsif Is_Scalar_Function (Decl) then + Predefined := Iir_Predefined_Ieee_1164_To_UX01_Log; + end if; + when Name_To_X01Z => + if Is_Vector_Function (Decl) then + -- TODO: distinguish slv/suv. + Predefined := Iir_Predefined_Ieee_1164_To_X01Z_Slv; + elsif Is_Scalar_Function (Decl) then + Predefined := Iir_Predefined_Ieee_1164_To_X01Z_Log; + end if; when Name_To_Hstring => Predefined := Iir_Predefined_Ieee_1164_To_Hstring; when Name_To_Ostring => @@ -413,8 +427,7 @@ package body Vhdl.Ieee.Std_Logic_1164 is Predefined := Iir_Predefined_Ieee_1164_Condition_Operator; when Name_Is_X => - Predefined := - Iir_Predefined_Ieee_1164_Scalar_Is_X; + Predefined := Iir_Predefined_Ieee_1164_Is_X_Log; when others => Predefined := Iir_Predefined_None; end case; @@ -452,8 +465,7 @@ package body Vhdl.Ieee.Std_Logic_1164 is when Name_Xnor => Predefined := Iir_Predefined_Ieee_1164_Xnor_Suv; when Name_Is_X => - Predefined := - Iir_Predefined_Ieee_1164_Scalar_Is_X; + Predefined := Iir_Predefined_Ieee_1164_Is_X_Slv; when others => Predefined := Iir_Predefined_None; end case; diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index f9b29cf78..c1868bfc7 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -5669,8 +5669,8 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_1164_To_UX01_Bv_Suv, Iir_Predefined_Ieee_1164_To_UX01_Bit_Log, - Iir_Predefined_Ieee_1164_Vector_Is_X, - Iir_Predefined_Ieee_1164_Scalar_Is_X, + Iir_Predefined_Ieee_1164_Is_X_Slv, + Iir_Predefined_Ieee_1164_Is_X_Log, Iir_Predefined_Ieee_1164_Rising_Edge, Iir_Predefined_Ieee_1164_Falling_Edge, -- cgit v1.2.3