From ac830367cc0c979472cabb9173102d591817f98c Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Mon, 20 Jan 2020 07:55:19 +0100 Subject: synth: add id_abs gate. For #1101 --- python/libghdl/thin/vhdl/nodes.py | 143 +++++++++++++++++++------------------- src/synth/ghdlsynth_gates.h | 15 ++-- src/synth/netlists-builders.adb | 1 + src/synth/netlists-disp_vhdl.adb | 2 + src/synth/netlists-gates.ads | 21 +++--- src/synth/synth-oper.adb | 2 + src/synth/synth-static_oper.adb | 2 + src/vhdl/vhdl-ieee-numeric.adb | 9 +++ src/vhdl/vhdl-nodes.ads | 2 + 9 files changed, 109 insertions(+), 88 deletions(-) diff --git a/python/libghdl/thin/vhdl/nodes.py b/python/libghdl/thin/vhdl/nodes.py index 2d690fd2f..5fce2f2e8 100644 --- a/python/libghdl/thin/vhdl/nodes.py +++ b/python/libghdl/thin/vhdl/nodes.py @@ -1275,77 +1275,78 @@ class Iir_Predefined: Ieee_Numeric_Std_Ror_Sgn_Nat = 292 Ieee_Numeric_Std_Not_Uns = 293 Ieee_Numeric_Std_Not_Sgn = 294 - Ieee_Numeric_Std_And_Uns_Uns = 295 - Ieee_Numeric_Std_And_Sgn_Sgn = 296 - Ieee_Numeric_Std_Or_Uns_Uns = 297 - Ieee_Numeric_Std_Or_Sgn_Sgn = 298 - Ieee_Numeric_Std_Nand_Uns_Uns = 299 - Ieee_Numeric_Std_Nand_Sgn_Sgn = 300 - Ieee_Numeric_Std_Nor_Uns_Uns = 301 - Ieee_Numeric_Std_Nor_Sgn_Sgn = 302 - Ieee_Numeric_Std_Xor_Uns_Uns = 303 - Ieee_Numeric_Std_Xor_Sgn_Sgn = 304 - Ieee_Numeric_Std_Xnor_Uns_Uns = 305 - Ieee_Numeric_Std_Xnor_Sgn_Sgn = 306 - Ieee_Numeric_Std_Neg_Uns = 307 - Ieee_Numeric_Std_Neg_Sgn = 308 - Ieee_Numeric_Std_Match_Log = 309 - Ieee_Numeric_Std_Match_Uns = 310 - Ieee_Numeric_Std_Match_Sgn = 311 - Ieee_Numeric_Std_Match_Slv = 312 - Ieee_Numeric_Std_Match_Suv = 313 - Ieee_Math_Real_Ceil = 314 - Ieee_Math_Real_Round = 315 - Ieee_Math_Real_Log2 = 316 - Ieee_Math_Real_Sin = 317 - Ieee_Math_Real_Cos = 318 - Ieee_Std_Logic_Unsigned_Add_Slv_Slv = 319 - Ieee_Std_Logic_Unsigned_Add_Slv_Int = 320 - Ieee_Std_Logic_Unsigned_Add_Int_Slv = 321 - Ieee_Std_Logic_Unsigned_Add_Slv_Sl = 322 - Ieee_Std_Logic_Unsigned_Add_Sl_Slv = 323 - Ieee_Std_Logic_Unsigned_Sub_Slv_Slv = 324 - Ieee_Std_Logic_Unsigned_Sub_Slv_Int = 325 - Ieee_Std_Logic_Unsigned_Sub_Int_Slv = 326 - Ieee_Std_Logic_Unsigned_Sub_Slv_Sl = 327 - Ieee_Std_Logic_Unsigned_Sub_Sl_Slv = 328 - Ieee_Std_Logic_Unsigned_Lt_Slv_Slv = 329 - Ieee_Std_Logic_Unsigned_Lt_Slv_Int = 330 - Ieee_Std_Logic_Unsigned_Lt_Int_Slv = 331 - Ieee_Std_Logic_Unsigned_Le_Slv_Slv = 332 - Ieee_Std_Logic_Unsigned_Le_Slv_Int = 333 - Ieee_Std_Logic_Unsigned_Le_Int_Slv = 334 - Ieee_Std_Logic_Unsigned_Gt_Slv_Slv = 335 - Ieee_Std_Logic_Unsigned_Gt_Slv_Int = 336 - Ieee_Std_Logic_Unsigned_Gt_Int_Slv = 337 - Ieee_Std_Logic_Unsigned_Ge_Slv_Slv = 338 - Ieee_Std_Logic_Unsigned_Ge_Slv_Int = 339 - Ieee_Std_Logic_Unsigned_Ge_Int_Slv = 340 - Ieee_Std_Logic_Unsigned_Eq_Slv_Slv = 341 - Ieee_Std_Logic_Unsigned_Eq_Slv_Int = 342 - Ieee_Std_Logic_Unsigned_Eq_Int_Slv = 343 - Ieee_Std_Logic_Unsigned_Ne_Slv_Slv = 344 - Ieee_Std_Logic_Unsigned_Ne_Slv_Int = 345 - Ieee_Std_Logic_Unsigned_Ne_Int_Slv = 346 - Ieee_Std_Logic_Unsigned_Conv_Integer = 347 - Ieee_Std_Logic_Signed_Add_Slv_Slv = 348 - Ieee_Std_Logic_Signed_Add_Slv_Int = 349 - Ieee_Std_Logic_Signed_Add_Int_Slv = 350 - Ieee_Std_Logic_Signed_Add_Slv_Sl = 351 - Ieee_Std_Logic_Signed_Add_Sl_Slv = 352 - Ieee_Std_Logic_Signed_Sub_Slv_Slv = 353 - Ieee_Std_Logic_Signed_Sub_Slv_Int = 354 - Ieee_Std_Logic_Signed_Sub_Int_Slv = 355 - Ieee_Std_Logic_Signed_Sub_Slv_Sl = 356 - Ieee_Std_Logic_Signed_Sub_Sl_Slv = 357 - Ieee_Std_Logic_Arith_Conv_Unsigned_Int = 358 - Ieee_Std_Logic_Arith_Conv_Unsigned_Uns = 359 - Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn = 360 - Ieee_Std_Logic_Arith_Conv_Unsigned_Log = 361 - Ieee_Std_Logic_Arith_Conv_Integer_Int = 362 - Ieee_Std_Logic_Arith_Conv_Integer_Uns = 363 - Ieee_Std_Logic_Arith_Conv_Integer_Sgn = 364 - Ieee_Std_Logic_Arith_Conv_Integer_Log = 365 + Ieee_Numeric_Std_Abs_Sgn = 295 + Ieee_Numeric_Std_And_Uns_Uns = 296 + Ieee_Numeric_Std_And_Sgn_Sgn = 297 + Ieee_Numeric_Std_Or_Uns_Uns = 298 + Ieee_Numeric_Std_Or_Sgn_Sgn = 299 + Ieee_Numeric_Std_Nand_Uns_Uns = 300 + Ieee_Numeric_Std_Nand_Sgn_Sgn = 301 + Ieee_Numeric_Std_Nor_Uns_Uns = 302 + Ieee_Numeric_Std_Nor_Sgn_Sgn = 303 + Ieee_Numeric_Std_Xor_Uns_Uns = 304 + Ieee_Numeric_Std_Xor_Sgn_Sgn = 305 + Ieee_Numeric_Std_Xnor_Uns_Uns = 306 + Ieee_Numeric_Std_Xnor_Sgn_Sgn = 307 + Ieee_Numeric_Std_Neg_Uns = 308 + Ieee_Numeric_Std_Neg_Sgn = 309 + Ieee_Numeric_Std_Match_Log = 310 + Ieee_Numeric_Std_Match_Uns = 311 + Ieee_Numeric_Std_Match_Sgn = 312 + Ieee_Numeric_Std_Match_Slv = 313 + Ieee_Numeric_Std_Match_Suv = 314 + Ieee_Math_Real_Ceil = 315 + Ieee_Math_Real_Round = 316 + Ieee_Math_Real_Log2 = 317 + Ieee_Math_Real_Sin = 318 + Ieee_Math_Real_Cos = 319 + Ieee_Std_Logic_Unsigned_Add_Slv_Slv = 320 + Ieee_Std_Logic_Unsigned_Add_Slv_Int = 321 + Ieee_Std_Logic_Unsigned_Add_Int_Slv = 322 + Ieee_Std_Logic_Unsigned_Add_Slv_Sl = 323 + Ieee_Std_Logic_Unsigned_Add_Sl_Slv = 324 + Ieee_Std_Logic_Unsigned_Sub_Slv_Slv = 325 + Ieee_Std_Logic_Unsigned_Sub_Slv_Int = 326 + Ieee_Std_Logic_Unsigned_Sub_Int_Slv = 327 + Ieee_Std_Logic_Unsigned_Sub_Slv_Sl = 328 + Ieee_Std_Logic_Unsigned_Sub_Sl_Slv = 329 + Ieee_Std_Logic_Unsigned_Lt_Slv_Slv = 330 + Ieee_Std_Logic_Unsigned_Lt_Slv_Int = 331 + Ieee_Std_Logic_Unsigned_Lt_Int_Slv = 332 + Ieee_Std_Logic_Unsigned_Le_Slv_Slv = 333 + Ieee_Std_Logic_Unsigned_Le_Slv_Int = 334 + Ieee_Std_Logic_Unsigned_Le_Int_Slv = 335 + Ieee_Std_Logic_Unsigned_Gt_Slv_Slv = 336 + Ieee_Std_Logic_Unsigned_Gt_Slv_Int = 337 + Ieee_Std_Logic_Unsigned_Gt_Int_Slv = 338 + Ieee_Std_Logic_Unsigned_Ge_Slv_Slv = 339 + Ieee_Std_Logic_Unsigned_Ge_Slv_Int = 340 + Ieee_Std_Logic_Unsigned_Ge_Int_Slv = 341 + Ieee_Std_Logic_Unsigned_Eq_Slv_Slv = 342 + Ieee_Std_Logic_Unsigned_Eq_Slv_Int = 343 + Ieee_Std_Logic_Unsigned_Eq_Int_Slv = 344 + Ieee_Std_Logic_Unsigned_Ne_Slv_Slv = 345 + Ieee_Std_Logic_Unsigned_Ne_Slv_Int = 346 + Ieee_Std_Logic_Unsigned_Ne_Int_Slv = 347 + Ieee_Std_Logic_Unsigned_Conv_Integer = 348 + Ieee_Std_Logic_Signed_Add_Slv_Slv = 349 + Ieee_Std_Logic_Signed_Add_Slv_Int = 350 + Ieee_Std_Logic_Signed_Add_Int_Slv = 351 + Ieee_Std_Logic_Signed_Add_Slv_Sl = 352 + Ieee_Std_Logic_Signed_Add_Sl_Slv = 353 + Ieee_Std_Logic_Signed_Sub_Slv_Slv = 354 + Ieee_Std_Logic_Signed_Sub_Slv_Int = 355 + Ieee_Std_Logic_Signed_Sub_Int_Slv = 356 + Ieee_Std_Logic_Signed_Sub_Slv_Sl = 357 + Ieee_Std_Logic_Signed_Sub_Sl_Slv = 358 + Ieee_Std_Logic_Arith_Conv_Unsigned_Int = 359 + Ieee_Std_Logic_Arith_Conv_Unsigned_Uns = 360 + Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn = 361 + Ieee_Std_Logic_Arith_Conv_Unsigned_Log = 362 + Ieee_Std_Logic_Arith_Conv_Integer_Int = 363 + Ieee_Std_Logic_Arith_Conv_Integer_Uns = 364 + Ieee_Std_Logic_Arith_Conv_Integer_Sgn = 365 + Ieee_Std_Logic_Arith_Conv_Integer_Log = 366 Get_Kind = libghdl.vhdl__nodes__get_kind Get_Location = libghdl.vhdl__nodes__get_location diff --git a/src/synth/ghdlsynth_gates.h b/src/synth/ghdlsynth_gates.h index 6530f300b..b215f9793 100644 --- a/src/synth/ghdlsynth_gates.h +++ b/src/synth/ghdlsynth_gates.h @@ -21,13 +21,14 @@ enum Module_Id { Id_Umod = 15, Id_Smod = 16, Id_Srem = 17, - Id_Lsl = 20, - Id_Lsr = 21, - Id_Asr = 22, - Id_Rol = 23, - Id_Ror = 24, - Id_Not = 25, - Id_Neg = 26, + Id_Not = 18, + Id_Neg = 19, + Id_Abs = 20, + Id_Lsl = 22, + Id_Lsr = 23, + Id_Asr = 24, + Id_Rol = 25, + Id_Ror = 26, Id_Eq = 27, Id_Ne = 28, Id_Ule = 29, diff --git a/src/synth/netlists-builders.adb b/src/synth/netlists-builders.adb index 9db99a20e..d869ebeba 100644 --- a/src/synth/netlists-builders.adb +++ b/src/synth/netlists-builders.adb @@ -597,6 +597,7 @@ package body Netlists.Builders is Create_Monadic_Module (Design, Res.M_Monadic (Id_Not), Name_Not, Id_Not); Create_Monadic_Module (Design, Res.M_Monadic (Id_Neg), Get_Identifier ("neg"), Id_Neg); + Create_Monadic_Module (Design, Res.M_Monadic (Id_Abs), Name_Abs, Id_Abs); Create_Compare_Module (Design, Res.M_Compare (Id_Eq), Get_Identifier ("eq"), Id_Eq); diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index 2bf9005cf..398e29a16 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -760,6 +760,8 @@ package body Netlists.Disp_Vhdl is Disp_Template (" \o0 <= not \i0;" & NL, Inst); when Id_Neg => Disp_Template (" \o0 <= std_logic_vector(-\si0);" & NL, Inst); + when Id_Abs=> + Disp_Template (" \o0 <= std_logic_vector(abs \si0);" & NL, Inst); when Id_Extract => Disp_Template (" \o0 <= ", Inst); Disp_Extract (Inst); diff --git a/src/synth/netlists-gates.ads b/src/synth/netlists-gates.ads index e185ee085..bb5e64204 100644 --- a/src/synth/netlists-gates.ads +++ b/src/synth/netlists-gates.ads @@ -43,28 +43,29 @@ package Netlists.Gates is subtype Dyadic_Module_Id is Module_Id range Id_And .. Id_Srem; + Id_Not : constant Module_Id := 18; + Id_Neg : constant Module_Id := 19; + Id_Abs : constant Module_Id := 20; + + subtype Monadic_Module_Id is Module_Id range Id_Not .. Id_Abs; + -- Logical and arithmetic shifts. -- FIXME: clarify right operand: width, large values - Id_Lsl : constant Module_Id := 20; - Id_Lsr : constant Module_Id := 21; - Id_Asr : constant Module_Id := 22; + Id_Lsl : constant Module_Id := 22; + Id_Lsr : constant Module_Id := 23; + Id_Asr : constant Module_Id := 24; subtype Shift_Module_Id is Module_Id range Id_Lsl .. Id_Asr; -- Rotations. -- FIXME: clarify right operand. - Id_Rol : constant Module_Id := 23; - Id_Ror : constant Module_Id := 24; + Id_Rol : constant Module_Id := 25; + Id_Ror : constant Module_Id := 26; subtype Rotate_Module_Id is Module_Id range Id_Lsl .. Id_Asr; subtype Shift_Rotate_Module_Id is Module_Id range Id_Lsl .. Id_Ror; - Id_Not : constant Module_Id := 25; - Id_Neg : constant Module_Id := 26; - - subtype Monadic_Module_Id is Module_Id range Id_Not .. Id_Neg; - Id_Eq : constant Module_Id := 27; Id_Ne : constant Module_Id := 28; Id_Ule : constant Module_Id := 29; diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb index a5dc07679..8f1a48011 100644 --- a/src/synth/synth-oper.adb +++ b/src/synth/synth-oper.adb @@ -929,6 +929,8 @@ package body Synth.Oper is when Iir_Predefined_Ieee_Numeric_Std_Neg_Uns | Iir_Predefined_Ieee_Numeric_Std_Neg_Sgn => return Synth_Vec_Monadic (Id_Neg); + when Iir_Predefined_Ieee_Numeric_Std_Abs_Sgn => + return Synth_Vec_Monadic (Id_Abs); when Iir_Predefined_Ieee_1164_Vector_And_Reduce => return Synth_Vec_Reduce_Monadic(Id_Red_And); when Iir_Predefined_Ieee_1164_Vector_Or_Reduce => diff --git a/src/synth/synth-static_oper.adb b/src/synth/synth-static_oper.adb index e366aefb9..c756bd3b0 100644 --- a/src/synth/synth-static_oper.adb +++ b/src/synth/synth-static_oper.adb @@ -514,6 +514,8 @@ package body Synth.Static_Oper is when Iir_Predefined_Integer_Negation => return Create_Value_Discrete (-Operand.Scal, Oper_Typ); + when Iir_Predefined_Integer_Absolute => + return Create_Value_Discrete (abs Operand.Scal, Oper_Typ); when Iir_Predefined_Floating_Negation => return Create_Value_Float (-Operand.Fp, Oper_Typ); diff --git a/src/vhdl/vhdl-ieee-numeric.adb b/src/vhdl/vhdl-ieee-numeric.adb index 9b93ffacc..10aa92d53 100644 --- a/src/vhdl/vhdl-ieee-numeric.adb +++ b/src/vhdl/vhdl-ieee-numeric.adb @@ -227,6 +227,13 @@ package body Vhdl.Ieee.Numeric is Pkg_Bit => (others => Iir_Predefined_None)); + Abs_Patterns : constant Unary_Pattern_Type := + (Pkg_Std => + (Type_Unsigned => Iir_Predefined_None, + Type_Signed => Iir_Predefined_Ieee_Numeric_Std_Abs_Sgn), + Pkg_Bit => + (others => Iir_Predefined_None)); + Not_Patterns : constant Unary_Pattern_Type := (Pkg_Std => (Type_Unsigned => Iir_Predefined_Ieee_Numeric_Std_Not_Uns, @@ -688,6 +695,8 @@ package body Vhdl.Ieee.Numeric is Handle_Unary (Neg_Patterns); when Name_Not => Handle_Unary (Not_Patterns); + when Name_Abs => + Handle_Unary (Abs_Patterns); when Name_To_Integer => Handle_To_Integer; when others => diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 0f9a4c213..1305632d7 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -5575,6 +5575,8 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Numeric_Std_Not_Uns, Iir_Predefined_Ieee_Numeric_Std_Not_Sgn, + Iir_Predefined_Ieee_Numeric_Std_Abs_Sgn, + Iir_Predefined_Ieee_Numeric_Std_And_Uns_Uns, Iir_Predefined_Ieee_Numeric_Std_And_Sgn_Sgn, -- cgit v1.2.3