From a94d2a0592495f3216c54b63e9591d6af760d999 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Thu, 3 Oct 2019 19:53:02 +0200
Subject: testsuite/synth: add a test for FF inference.

---
 testsuite/synth/issue963/ent2.vhdl    | 34 ++++++++++++
 testsuite/synth/issue963/tb_ent2.vhdl | 98 +++++++++++++++++++++++++++++++++++
 testsuite/synth/issue963/testsuite.sh |  2 +-
 3 files changed, 133 insertions(+), 1 deletion(-)
 create mode 100644 testsuite/synth/issue963/ent2.vhdl
 create mode 100644 testsuite/synth/issue963/tb_ent2.vhdl

diff --git a/testsuite/synth/issue963/ent2.vhdl b/testsuite/synth/issue963/ent2.vhdl
new file mode 100644
index 000000000..7067debe6
--- /dev/null
+++ b/testsuite/synth/issue963/ent2.vhdl
@@ -0,0 +1,34 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity ent2 is
+    port (
+        clk : in std_logic;
+        set_7 : in std_logic;
+        set_f : in std_logic;
+        set_a : in std_logic;
+        set_0 : in std_logic;
+        q : out std_logic_vector(3 downto 0)
+    );
+end;
+
+architecture a of ent2 is
+    signal s : unsigned(3 downto 0);
+begin
+    process(clk, set_0, set_a, set_f, set_7)
+    begin
+        if set_0 = '1' then
+            s <= x"0";
+        elsif set_a = '1' then
+            s <= x"a";
+        elsif set_f = '1' then
+            s <= x"f";
+        elsif set_7 = '1' then
+            s <= x"7";
+        elsif rising_edge(clk) then
+            s <= s + 1;
+        end if;
+    end process;
+    q <= std_logic_vector(s);
+end;
diff --git a/testsuite/synth/issue963/tb_ent2.vhdl b/testsuite/synth/issue963/tb_ent2.vhdl
new file mode 100644
index 000000000..daf1865cb
--- /dev/null
+++ b/testsuite/synth/issue963/tb_ent2.vhdl
@@ -0,0 +1,98 @@
+entity tb_ent2 is
+end tb_ent2;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_ent2 is
+  signal clk : std_logic;
+  signal dout : std_logic_vector(3 downto 0);
+  signal set_0 : std_logic;
+  signal set_a : std_logic;
+  signal set_f : std_logic;
+  signal set_7 : std_logic;
+begin
+  dut: entity work.ent2
+    port map (
+      set_0 => set_0,
+      set_a => set_a,
+      set_f => set_f,
+      set_7 => set_7,
+      q => dout,
+      clk => clk);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    set_0 <= '1';
+    set_a <= '0';
+    set_f <= '0';
+    set_7 <= '0';
+    pulse;
+    assert dout = x"0" severity failure;
+
+    set_0 <= '0';
+    set_a <= '0';
+    set_f <= '0';
+    set_7 <= '0';
+    pulse;
+    assert dout = x"1" severity failure;
+
+    set_0 <= '0';
+    set_a <= '0';
+    set_f <= '0';
+    set_7 <= '0';
+    pulse;
+    assert dout = x"2" severity failure;
+
+    set_0 <= '0';
+    set_a <= '1';
+    set_f <= '0';
+    set_7 <= '0';
+    pulse;
+    assert dout = x"a" severity failure;
+
+    set_0 <= '0';
+    set_a <= '0';
+    set_f <= '0';
+    set_7 <= '0';
+    pulse;
+    assert dout = x"b" severity failure;
+
+    set_0 <= '0';
+    set_a <= '0';
+    set_f <= '1';
+    set_7 <= '0';
+    pulse;
+    assert dout = x"f" severity failure;
+
+    set_0 <= '0';
+    set_a <= '0';
+    set_f <= '0';
+    set_7 <= '1';
+    pulse;
+    assert dout = x"7" severity failure;
+
+    set_0 <= '1';
+    set_a <= '0';
+    set_f <= '0';
+    set_7 <= '1';
+    pulse;
+    assert dout = x"0" severity failure;
+
+    set_0 <= '0';
+    set_a <= '1';
+    set_f <= '0';
+    set_7 <= '1';
+    pulse;
+    assert dout = x"a" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue963/testsuite.sh b/testsuite/synth/issue963/testsuite.sh
index e30a741e0..33ea4d242 100755
--- a/testsuite/synth/issue963/testsuite.sh
+++ b/testsuite/synth/issue963/testsuite.sh
@@ -2,7 +2,7 @@
 
 . ../../testenv.sh
 
-for t in ent; do
+for t in ent ent2; do
     analyze $t.vhdl tb_$t.vhdl
     elab_simulate tb_$t
     clean
-- 
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