From 97c46f4c2f3efe2bba45edc50e98aa968155caec Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Fri, 27 May 2016 06:39:52 +0200
Subject: Add testcase for issue73.
---
testsuite/gna/issue73/testsuite.sh | 10 ++++++++++
testsuite/gna/issue73/x.vhdl | 34 ++++++++++++++++++++++++++++++++++
2 files changed, 44 insertions(+)
create mode 100755 testsuite/gna/issue73/testsuite.sh
create mode 100644 testsuite/gna/issue73/x.vhdl
diff --git a/testsuite/gna/issue73/testsuite.sh b/testsuite/gna/issue73/testsuite.sh
new file mode 100755
index 000000000..f75225062
--- /dev/null
+++ b/testsuite/gna/issue73/testsuite.sh
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze x.vhdl
+elab_simulate test
+
+clean
+
+echo "Test successful"
diff --git a/testsuite/gna/issue73/x.vhdl b/testsuite/gna/issue73/x.vhdl
new file mode 100644
index 000000000..afb27eec2
--- /dev/null
+++ b/testsuite/gna/issue73/x.vhdl
@@ -0,0 +1,34 @@
+entity test is
+end entity test;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture test of test is
+
+begin
+
+ p: process is
+
+ subtype xa_t is std_ulogic_vector(3 downto 0);
+ subtype ya_t is std_ulogic_vector(1 downto 0);
+
+ procedure x(constant a : xa_t) is
+ begin
+ for i in a'range loop
+ report "x.a(" & integer'image(i) & "): " & std_ulogic'image(a(i)) severity note;
+ end loop;
+ end procedure x;
+
+ procedure y(constant a : in ya_t) is
+ begin
+ x(a(1 downto 0) => a,
+ a(3 downto 2) => (others => '0'));
+ end procedure y;
+
+ begin
+ y(a => "11");
+ wait;
+ end process p;
+
+end architecture test;
--
cgit v1.2.3