From 9624f0ce08849f8cf14fe81416496417b4754d9d Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Fri, 16 Nov 2018 20:30:58 +0100
Subject: sem: clear default PSL clock at beginning of architecture.

---
 src/vhdl/sem.adb | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/vhdl/sem.adb b/src/vhdl/sem.adb
index 7408d05e7..ecb6377af 100644
--- a/src/vhdl/sem.adb
+++ b/src/vhdl/sem.adb
@@ -204,7 +204,10 @@ package body Sem is
       if Vhdl_Std = Vhdl_02 then
          Open_Declarative_Region;
       end if;
+
+      Current_Psl_Default_Clock := Null_Iir;
       Sem_Block (Arch);
+
       if Vhdl_Std = Vhdl_02 then
          Close_Declarative_Region;
       end if;
-- 
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