From 930bfe7d5aefbb88e80a92991a372c9e822558b0 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Tue, 7 Sep 2021 21:19:42 +0200
Subject: testsuite/gna: add a test for #737

---
 testsuite/gna/issue737/ent.vhdl     | 11 +++++++++++
 testsuite/gna/issue737/ent1.vhdl    | 12 ++++++++++++
 testsuite/gna/issue737/ent2.vhdl    | 14 ++++++++++++++
 testsuite/gna/issue737/ent3.vhdl    | 14 ++++++++++++++
 testsuite/gna/issue737/ent4.vhdl    | 13 +++++++++++++
 testsuite/gna/issue737/testsuite.sh | 24 ++++++++++++++++++++++++
 6 files changed, 88 insertions(+)
 create mode 100644 testsuite/gna/issue737/ent.vhdl
 create mode 100644 testsuite/gna/issue737/ent1.vhdl
 create mode 100644 testsuite/gna/issue737/ent2.vhdl
 create mode 100644 testsuite/gna/issue737/ent3.vhdl
 create mode 100644 testsuite/gna/issue737/ent4.vhdl
 create mode 100755 testsuite/gna/issue737/testsuite.sh

diff --git a/testsuite/gna/issue737/ent.vhdl b/testsuite/gna/issue737/ent.vhdl
new file mode 100644
index 000000000..988acb082
--- /dev/null
+++ b/testsuite/gna/issue737/ent.vhdl
@@ -0,0 +1,11 @@
+entity ent is
+end entity;
+
+architecture impl of ent is
+	type bitvv is array(natural range <>) of bit_vector;
+	signal foo: bitvv(2 downto 0)(0 downto 0);
+begin
+
+foo <= foo(1 downto 0) & foo(2);
+
+end architecture;
diff --git a/testsuite/gna/issue737/ent1.vhdl b/testsuite/gna/issue737/ent1.vhdl
new file mode 100644
index 000000000..71a98b1b6
--- /dev/null
+++ b/testsuite/gna/issue737/ent1.vhdl
@@ -0,0 +1,12 @@
+entity ent1 is
+end entity;
+
+architecture impl of ent1 is
+	type bitvv is array(natural range <>) of bit_vector;
+	signal foo: bitvv(2 downto 0)(0 downto 0);
+        signal foo1 : bitvv(1 downto 0)(0 downto 0);
+begin
+
+foo1 <= foo(1 downto 0);
+
+end architecture;
diff --git a/testsuite/gna/issue737/ent2.vhdl b/testsuite/gna/issue737/ent2.vhdl
new file mode 100644
index 000000000..fe4f49145
--- /dev/null
+++ b/testsuite/gna/issue737/ent2.vhdl
@@ -0,0 +1,14 @@
+entity ent2 is
+end entity;
+
+architecture impl of ent2 is
+	type bitvv is array(natural range <>) of bit_vector;
+	signal foo: bitvv(2 downto 0)(0 downto 0);
+begin
+
+foo <= (
+	2 downto 1 => foo(1 downto 0),
+	0 => foo(2)
+);
+
+end architecture;
diff --git a/testsuite/gna/issue737/ent3.vhdl b/testsuite/gna/issue737/ent3.vhdl
new file mode 100644
index 000000000..39d5e3ad9
--- /dev/null
+++ b/testsuite/gna/issue737/ent3.vhdl
@@ -0,0 +1,14 @@
+entity ent3 is
+end entity;
+
+architecture impl of ent3 is
+	type bitvv is array(natural range <>) of bit_vector;
+	signal foo: bitvv(2 downto 0)(0 downto 0);
+begin
+
+foo <= bitvv'(
+	2 downto 1 => foo(1 downto 0),
+	0 => foo(2)
+);
+
+end architecture;
diff --git a/testsuite/gna/issue737/ent4.vhdl b/testsuite/gna/issue737/ent4.vhdl
new file mode 100644
index 000000000..6935ac99b
--- /dev/null
+++ b/testsuite/gna/issue737/ent4.vhdl
@@ -0,0 +1,13 @@
+entity ent4 is
+end entity;
+
+architecture impl of ent4 is
+	type bitvv is array(natural range <>) of bit_vector;
+	signal foo: bitvv(2 downto 0)(0 downto 0);
+	signal bar: bitvv(1 downto 0)(0 downto 0);
+begin
+
+foo(2 downto 1) <= bar;
+foo(0) <= foo(2);
+
+end architecture;
diff --git a/testsuite/gna/issue737/testsuite.sh b/testsuite/gna/issue737/testsuite.sh
new file mode 100755
index 000000000..5212b92a9
--- /dev/null
+++ b/testsuite/gna/issue737/testsuite.sh
@@ -0,0 +1,24 @@
+#! /bin/sh
+
+#exit 0
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+
+analyze ent.vhdl
+elab_simulate ent
+
+analyze ent1.vhdl
+elab_simulate ent1
+
+analyze ent2.vhdl
+elab_simulate ent2
+
+#TODO: ent3
+
+analyze ent4.vhdl
+elab_simulate ent4
+
+clean
+
+echo "Test successful"
-- 
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