From 90184a346889e3d9392fba6f71829b0a8893d70c Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Wed, 5 Aug 2020 18:33:55 +0200
Subject: testsuite/gna: add a test for #1131

---
 testsuite/gna/issue1131/dut.vhdl     | 27 +++++++++++++++++++++++++++
 testsuite/gna/issue1131/repro.vhdl   | 18 ++++++++++++++++++
 testsuite/gna/issue1131/repro1.vhdl  | 18 ++++++++++++++++++
 testsuite/gna/issue1131/repro2.vhdl  | 29 +++++++++++++++++++++++++++++
 testsuite/gna/issue1131/testsuite.sh | 20 ++++++++++++++++++++
 5 files changed, 112 insertions(+)
 create mode 100644 testsuite/gna/issue1131/dut.vhdl
 create mode 100644 testsuite/gna/issue1131/repro.vhdl
 create mode 100644 testsuite/gna/issue1131/repro1.vhdl
 create mode 100644 testsuite/gna/issue1131/repro2.vhdl
 create mode 100755 testsuite/gna/issue1131/testsuite.sh

diff --git a/testsuite/gna/issue1131/dut.vhdl b/testsuite/gna/issue1131/dut.vhdl
new file mode 100644
index 000000000..0bbfa9d67
--- /dev/null
+++ b/testsuite/gna/issue1131/dut.vhdl
@@ -0,0 +1,27 @@
+library IEEE;
+use IEEE.Std_Logic_1164.all;
+
+entity DUT is
+	generic (
+		BUS_WIDTH : integer := 64;
+		OTHER_WIDTH : integer := 4
+	);
+	port (
+		Clk : in std_logic;
+		Reset : in std_logic
+	);
+end entity;
+
+architecture Behavioural of DUT is
+	type BusT is record
+		A : std_logic_vector;
+		F : std_logic_vector;
+	end record;
+
+	signal BusInst : BusT(
+		A(BUS_WIDTH-1 downto 0),
+		F(3 downto 0)
+	);
+begin
+
+end architecture;
diff --git a/testsuite/gna/issue1131/repro.vhdl b/testsuite/gna/issue1131/repro.vhdl
new file mode 100644
index 000000000..9a56e95fd
--- /dev/null
+++ b/testsuite/gna/issue1131/repro.vhdl
@@ -0,0 +1,18 @@
+entity repro is
+	generic (
+		BUS_WIDTH : integer := 8);
+end entity;
+
+architecture Behav of repro is
+	type BusT is record
+		A : bit_vector;
+		F : bit_vector;
+	end record;
+
+	signal BusInst : BusT(
+		A(BUS_WIDTH-1 downto 0),
+		F(3 downto 0)
+	);
+begin
+
+end architecture;
diff --git a/testsuite/gna/issue1131/repro1.vhdl b/testsuite/gna/issue1131/repro1.vhdl
new file mode 100644
index 000000000..934f800d7
--- /dev/null
+++ b/testsuite/gna/issue1131/repro1.vhdl
@@ -0,0 +1,18 @@
+entity repro1 is
+	generic (
+		BUS_WIDTH : integer := 8);
+end entity;
+
+architecture Behav of repro1 is
+	type BusT is record
+		A : bit_vector;
+		F : bit_vector;
+	end record;
+
+	signal BusInst : BusT(
+		A(BUS_WIDTH-1 downto 0),
+		F(3 downto 0)
+	);
+begin
+
+end architecture;
diff --git a/testsuite/gna/issue1131/repro2.vhdl b/testsuite/gna/issue1131/repro2.vhdl
new file mode 100644
index 000000000..77d1a1f2e
--- /dev/null
+++ b/testsuite/gna/issue1131/repro2.vhdl
@@ -0,0 +1,29 @@
+library IEEE;
+use IEEE.Std_Logic_1164.all;
+
+entity repro2 is
+	generic (
+		BUS_WIDTH : integer := 8
+	);
+end entity;
+
+architecture Behav of repro2 is
+	type BusT is record
+		A : std_logic_vector;
+		F : std_logic_vector;
+	end record;
+
+	signal BusInst : BusT(
+		A(BUS_WIDTH-1 downto 0),
+		F(3 downto 0)
+                );
+
+        type bust_Arr is array (natural range <>) of bust;
+
+        subtype my_bust_arr is bust_arr (0 to 1)(a(3 downto 0), f(2 downto 0));
+
+        signal barr1 : my_bust_arr;
+        signal barr2 : bust_arr (1 downto 0)(a(3 downto 0), f(3 downto 0));
+begin
+
+end architecture;
diff --git a/testsuite/gna/issue1131/testsuite.sh b/testsuite/gna/issue1131/testsuite.sh
new file mode 100755
index 000000000..f5ecbbc3e
--- /dev/null
+++ b/testsuite/gna/issue1131/testsuite.sh
@@ -0,0 +1,20 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+
+for f in dut repro2; do
+  analyze $f.vhdl
+  elab $f
+
+  if ghdl_has_feature $f ghw; then
+    simulate $f --dump-rti
+    simulate $f --wave=$f.ghw
+    rm -f $f.ghw
+  fi
+done
+
+clean
+
+echo "Test successful"
-- 
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