From 88425cb365578cacd46939d93f837b2ac7b0d5e8 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Mon, 6 Dec 2021 20:47:04 +0100
Subject: synth: add --latches option to enable latches.  Fix #938

---
 src/ghdldrv/ghdlsynth.adb        | 3 +++
 src/synth/netlists-inference.adb | 6 +++++-
 src/synth/netlists-inference.ads | 3 +++
 3 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/src/ghdldrv/ghdlsynth.adb b/src/ghdldrv/ghdlsynth.adb
index 669588132..cfc5f281b 100644
--- a/src/ghdldrv/ghdlsynth.adb
+++ b/src/ghdldrv/ghdlsynth.adb
@@ -45,6 +45,7 @@ with Netlists.Disp_Vhdl;
 with Netlists.Disp_Verilog;
 with Netlists.Disp_Dot;
 with Netlists.Errors;
+with Netlists.Inference;
 
 with Elab.Vhdl_Context; use Elab.Vhdl_Context;
 with Elab.Vhdl_Insts;
@@ -155,6 +156,8 @@ package body Ghdlsynth is
          Synth.Flags.Flag_Formal := False;
       elsif Option = "--formal" then
          Synth.Flags.Flag_Formal := True;
+      elsif Option = "--latches" then
+         Netlists.Inference.Flag_Latches := True;
       elsif Option = "--no-assert-cover" then
          Synth.Flags.Flag_Assert_Cover := False;
       elsif Option = "--assert-cover" then
diff --git a/src/synth/netlists-inference.adb b/src/synth/netlists-inference.adb
index 6da07e19a..383211684 100644
--- a/src/synth/netlists-inference.adb
+++ b/src/synth/netlists-inference.adb
@@ -780,7 +780,11 @@ package body Netlists.Inference is
       else
          Name := Get_Instance_Name (Get_Net_Parent (Prev_Val));
       end if;
-      Error_Msg_Synth (Loc, "latch infered for net %n", +Name);
+
+      if not Flag_Latches then
+         Error_Msg_Synth
+           (Loc, "latch infered for net %n (use --latches)", +Name);
+      end if;
 
       return Val;
    end Infere_Latch;
diff --git a/src/synth/netlists-inference.ads b/src/synth/netlists-inference.ads
index 61eab9fb2..ae671a0ac 100644
--- a/src/synth/netlists-inference.ads
+++ b/src/synth/netlists-inference.ads
@@ -20,6 +20,9 @@ with Netlists; use Netlists;
 with Netlists.Builders; use Netlists.Builders;
 
 package Netlists.Inference is
+   --  If True, latches are allowed.
+   Flag_Latches : Boolean := False;
+
    --  Walk the And-net N, and extract clock (posedge/negedge) if found.
    --  ENABLE is N without the clock.
    --  If not found, CLK and ENABLE are set to No_Net.
-- 
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