From 81ad114f07bebf66d337049303998879d1881ccd Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sun, 12 Apr 2020 23:29:14 +0200
Subject: testsuite/synth: add test for #1217

---
 testsuite/synth/issue1217/tb_top.vhdl  | 21 +++++++++++++++++++++
 testsuite/synth/issue1217/testsuite.sh |  7 +++++++
 testsuite/synth/issue1217/top.vhdl     | 26 ++++++++++++++++++++++++++
 3 files changed, 54 insertions(+)
 create mode 100644 testsuite/synth/issue1217/tb_top.vhdl
 create mode 100755 testsuite/synth/issue1217/testsuite.sh
 create mode 100644 testsuite/synth/issue1217/top.vhdl

diff --git a/testsuite/synth/issue1217/tb_top.vhdl b/testsuite/synth/issue1217/tb_top.vhdl
new file mode 100644
index 000000000..df2e7e8a1
--- /dev/null
+++ b/testsuite/synth/issue1217/tb_top.vhdl
@@ -0,0 +1,21 @@
+entity tb_top is
+end tb_top;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_top is
+  signal p : std_logic;
+  signal q : std_logic;
+begin
+  dut: entity work.top
+    port map (p, q);
+
+  process
+  begin
+    wait for 1 ns;
+    assert p = '0' severity failure;
+    assert q = '1' severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1217/testsuite.sh b/testsuite/synth/issue1217/testsuite.sh
new file mode 100755
index 000000000..60399a753
--- /dev/null
+++ b/testsuite/synth/issue1217/testsuite.sh
@@ -0,0 +1,7 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_tb top
+
+echo "Test successful"
diff --git a/testsuite/synth/issue1217/top.vhdl b/testsuite/synth/issue1217/top.vhdl
new file mode 100644
index 000000000..98305667c
--- /dev/null
+++ b/testsuite/synth/issue1217/top.vhdl
@@ -0,0 +1,26 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity top is
+port (p, q : out std_logic);
+end entity;
+
+architecture arch of top is
+	type subrecord_r is record
+		c : std_logic;
+		d : std_logic;
+	end record;
+	type record_r is record
+		s : subrecord_r;
+		a : std_logic;
+		b : std_logic;
+	end record;
+	signal s : subrecord_r;
+	signal r : record_r;
+begin
+	s <= ('0', '0');
+	r <= (s, '0', '1');
+	p <= r.a;
+	q <= r.b;
+end architecture;
-- 
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