From 7bb42dba484fcbec66a97f613fa07a0299320443 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Thu, 9 Apr 2020 22:04:30 +0200 Subject: testsuite/synth: add a case for #1181 --- testsuite/synth/issue1181/bug.vhdl | 22 ++++++++++++++++++++++ testsuite/synth/issue1181/testsuite.sh | 9 +++++++++ 2 files changed, 31 insertions(+) create mode 100644 testsuite/synth/issue1181/bug.vhdl create mode 100755 testsuite/synth/issue1181/testsuite.sh diff --git a/testsuite/synth/issue1181/bug.vhdl b/testsuite/synth/issue1181/bug.vhdl new file mode 100644 index 000000000..39a943d08 --- /dev/null +++ b/testsuite/synth/issue1181/bug.vhdl @@ -0,0 +1,22 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity bug is + port( + dummy : in std_ulogic + ); +end bug; + +architecture behav of bug is +begin + process(all) + variable index : integer; + begin + index := 10; + if index > 3 then + -- index := index-1; + end if; + end process; + +end architecture; diff --git a/testsuite/synth/issue1181/testsuite.sh b/testsuite/synth/issue1181/testsuite.sh new file mode 100755 index 000000000..4c4a4df76 --- /dev/null +++ b/testsuite/synth/issue1181/testsuite.sh @@ -0,0 +1,9 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=--std=08 +synth_analyze bug +clean + +echo "Test successful" -- cgit v1.2.3