From 7548e438616dfc9fcfd05d1df8d6b4d88796e279 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sat, 17 Sep 2022 11:24:20 +0200
Subject: synth: finalize files

---
 src/synth/elab-vhdl_files.adb  | 30 +++++++++++++++++++++++++++---
 src/synth/elab-vhdl_files.ads  |  1 +
 src/synth/synth-vhdl_decls.adb |  3 ++-
 3 files changed, 30 insertions(+), 4 deletions(-)

diff --git a/src/synth/elab-vhdl_files.adb b/src/synth/elab-vhdl_files.adb
index 8fe2fef93..be00296af 100644
--- a/src/synth/elab-vhdl_files.adb
+++ b/src/synth/elab-vhdl_files.adb
@@ -355,7 +355,8 @@ package body Elab.Vhdl_Files is
       case Status is
          when Op_Ok =>
             Vstatus := Open_Ok;
-         when Op_Status_Error =>
+         when Op_Status_Error
+           | Op_Not_Closed =>
             Vstatus := Status_Error;
          when Op_Mode_Error =>
             Vstatus := Mode_Error;
@@ -372,8 +373,7 @@ package body Elab.Vhdl_Files is
            | Op_Read_Error
            | Op_Write_Error
            | Op_Bad_Index
-           | Op_Bad_Mode
-           | Op_Not_Closed =>
+           | Op_Bad_Mode =>
             raise File_Execution_Error;
       end case;
 
@@ -664,4 +664,28 @@ package body Elab.Vhdl_Files is
          File_Write_Value (File, (Value.Typ, Value.Val.Mem), Loc);
       end if;
    end Synth_File_Write;
+
+   procedure Finalize_File (Syn_Inst : Synth_Instance_Acc; Decl : Node)
+   is
+      File : constant File_Index := Get_Value (Syn_Inst, Decl).Val.File;
+      Is_Text : constant Boolean := Get_Text_File_Flag (Get_Type (Decl));
+      Status : Op_Status;
+   begin
+      if Is_Text then
+         Ghdl_Text_File_Close (File, Status);
+      else
+         Ghdl_File_Close (File, Status);
+      end if;
+      if Status /= Op_Ok then
+         File_Error (Decl, Status);
+      end if;
+      if Is_Text then
+         Ghdl_Text_File_Finalize (File, Status);
+      else
+         Ghdl_File_Finalize (File, Status);
+      end if;
+      if Status /= Op_Ok then
+         File_Error (Decl, Status);
+      end if;
+   end Finalize_File;
 end Elab.Vhdl_Files;
diff --git a/src/synth/elab-vhdl_files.ads b/src/synth/elab-vhdl_files.ads
index 7aaf3c37b..c0d97790f 100644
--- a/src/synth/elab-vhdl_files.ads
+++ b/src/synth/elab-vhdl_files.ads
@@ -31,6 +31,7 @@ package Elab.Vhdl_Files is
 
    function Elaborate_File_Declaration
      (Syn_Inst : Synth_Instance_Acc; Decl : Node) return File_Index;
+   procedure Finalize_File (Syn_Inst : Synth_Instance_Acc; Decl : Node);
 
    function Endfile (F : File_Index; Loc : Node) return Boolean;
 
diff --git a/src/synth/synth-vhdl_decls.adb b/src/synth/synth-vhdl_decls.adb
index c3945a82c..24add2a12 100644
--- a/src/synth/synth-vhdl_decls.adb
+++ b/src/synth/synth-vhdl_decls.adb
@@ -33,6 +33,7 @@ with Vhdl.Std_Package;
 with Elab.Vhdl_Values; use Elab.Vhdl_Values;
 with Elab.Vhdl_Types; use Elab.Vhdl_Types;
 with Elab.Vhdl_Decls; use Elab.Vhdl_Decls;
+with Elab.Vhdl_Files;
 
 with Synth.Vhdl_Environment; use Synth.Vhdl_Environment.Env;
 with Synth.Vhdl_Expr; use Synth.Vhdl_Expr;
@@ -793,7 +794,7 @@ package body Synth.Vhdl_Decls is
          when Iir_Kind_Component_Declaration =>
             null;
          when Iir_Kind_File_Declaration =>
-            null;
+            Elab.Vhdl_Files.Finalize_File (Syn_Inst, Decl);
          when Iir_Kind_Configuration_Specification =>
             null;
          when Iir_Kind_Psl_Default_Clock =>
-- 
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