From 6782adcb601253cd9836302ba8be4ea500b7911e Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Sat, 11 Jan 2020 17:27:38 +0100 Subject: testsuite/synth: add a test for #1083 --- testsuite/synth/issue1083/test.vhdl | 24 ++++++++++++++++++++++++ testsuite/synth/issue1083/testsuite.sh | 11 +++++++++++ 2 files changed, 35 insertions(+) create mode 100644 testsuite/synth/issue1083/test.vhdl create mode 100755 testsuite/synth/issue1083/testsuite.sh diff --git a/testsuite/synth/issue1083/test.vhdl b/testsuite/synth/issue1083/test.vhdl new file mode 100644 index 000000000..a08c5872a --- /dev/null +++ b/testsuite/synth/issue1083/test.vhdl @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity test is + port ( + a_in : in std_ulogic_vector(9 downto 0); + b_out : out std_ulogic + ); +end entity test; + +architecture behaviour of test is + type array_type_t is array(0 to 1023) of std_ulogic; + + constant ary : array_type_t := ( + 2#0000000010# => '1', + 2#0100000010# => '1', + 2#1000000010# => '1', + 2#1100000010# => '1', + others => '0' + ); +begin + b_out <= ary(to_integer(unsigned(a_in))); +end architecture behaviour; diff --git a/testsuite/synth/issue1083/testsuite.sh b/testsuite/synth/issue1083/testsuite.sh new file mode 100755 index 000000000..a4c28bcd4 --- /dev/null +++ b/testsuite/synth/issue1083/testsuite.sh @@ -0,0 +1,11 @@ +#! /bin/sh + +. ../../testenv.sh + +for t in test; do + synth $t.vhdl -e $t > syn_$t.vhdl + analyze syn_$t.vhdl + clean +done + +echo "Test successful" -- cgit v1.2.3