From 630b01519388cbda2929ccb1928f20806dc8ee17 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Wed, 27 Apr 2022 09:46:49 +0200 Subject: synth-vhdl_stmts: add implicit conversion for cond assignment Fix #2042 (The first issue only) --- src/synth/synth-vhdl_stmts.adb | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb index f6624b55e..434646f99 100644 --- a/src/synth/synth-vhdl_stmts.adb +++ b/src/synth/synth-vhdl_stmts.adb @@ -723,10 +723,15 @@ package body Synth.Vhdl_Stmts is while Ce /= Null_Node loop Val := Synth_Expression_With_Type (C.Inst, Get_Expression (Ce), Targ_Type); + -- Convert to the target subtype so that all the conditional + -- expressions have the same width. + Val := Synth_Subtype_Conversion (Ctxt, Val, Targ_Type, False, Ce); V := Get_Net (Ctxt, Val); Cond := Get_Condition (Ce); if Cond /= Null_Node then Cond_Val := Synth_Expression (C.Inst, Cond); + -- Note: as one input of the mux2 is not connected, there is no + -- check on inputs width. V := Build_Mux2 (Ctxt, Get_Net (Ctxt, Cond_Val), No_Net, V); Set_Location (V, Ce); end if; -- cgit v1.2.3