From 5cbfa82ebe90ac1016899c9cbecbaf07daa7e588 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Wed, 19 Oct 2022 05:58:32 +0200 Subject: synth-vhdl_eval: handle std_logic_misc reduce functions --- src/synth/synth-vhdl_eval.adb | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/src/synth/synth-vhdl_eval.adb b/src/synth/synth-vhdl_eval.adb index 1817794cc..260af0047 100644 --- a/src/synth/synth-vhdl_eval.adb +++ b/src/synth/synth-vhdl_eval.adb @@ -2932,6 +2932,33 @@ package body Synth.Vhdl_Eval is (Get_Memtyp (Param1), Read_Discrete (Param2), Std_Ulogic'Pos('0'), Iir_Predefined_Array_Sra); + when Iir_Predefined_Ieee_Std_Logic_Misc_And_Reduce_Slv + | Iir_Predefined_Ieee_Std_Logic_Misc_And_Reduce_Suv => + return Eval_Vector_Reduce + ('1', Get_Memtyp (Param1), And_Table, False); + when Iir_Predefined_Ieee_Std_Logic_Misc_Nand_Reduce_Slv + | Iir_Predefined_Ieee_Std_Logic_Misc_Nand_Reduce_Suv => + return Eval_Vector_Reduce + ('1', Get_Memtyp (Param1), And_Table, True); + + when Iir_Predefined_Ieee_Std_Logic_Misc_Or_Reduce_Slv + | Iir_Predefined_Ieee_Std_Logic_Misc_Or_Reduce_Suv => + return Eval_Vector_Reduce + ('0', Get_Memtyp (Param1), Or_Table, False); + when Iir_Predefined_Ieee_Std_Logic_Misc_Nor_Reduce_Slv + | Iir_Predefined_Ieee_Std_Logic_Misc_Nor_Reduce_Suv => + return Eval_Vector_Reduce + ('0', Get_Memtyp (Param1), Or_Table, True); + + when Iir_Predefined_Ieee_Std_Logic_Misc_Xor_Reduce_Slv + | Iir_Predefined_Ieee_Std_Logic_Misc_Xor_Reduce_Suv => + return Eval_Vector_Reduce + ('0', Get_Memtyp (Param1), Xor_Table, False); + when Iir_Predefined_Ieee_Std_Logic_Misc_Xnor_Reduce_Slv + | Iir_Predefined_Ieee_Std_Logic_Misc_Xnor_Reduce_Suv => + return Eval_Vector_Reduce + ('0', Get_Memtyp (Param1), Xor_Table, True); + when Iir_Predefined_Ieee_Math_Real_Sign => declare Val : constant Fp64 := Read_Fp64 (Param1); -- cgit v1.2.3