From 5853a37df7c9468a01d62f7b2eeee7d9773e72ca Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 19 Dec 2022 22:07:02 +0100 Subject: Restructured test example sourcefiles. --- testsuite/pyunit/SimpleEntity.vhdl | 55 --------- testsuite/pyunit/SimplePackage.vhdl | 15 --- testsuite/pyunit/dom/Simple.py | 140 +++++++++++++++++++++++ testsuite/pyunit/dom/SimpleEntity.py | 91 --------------- testsuite/pyunit/dom/examples/SimpleEntity.vhdl | 55 +++++++++ testsuite/pyunit/dom/examples/SimplePackage.vhdl | 28 +++++ 6 files changed, 223 insertions(+), 161 deletions(-) delete mode 100644 testsuite/pyunit/SimpleEntity.vhdl delete mode 100644 testsuite/pyunit/SimplePackage.vhdl create mode 100644 testsuite/pyunit/dom/Simple.py delete mode 100644 testsuite/pyunit/dom/SimpleEntity.py create mode 100644 testsuite/pyunit/dom/examples/SimpleEntity.vhdl create mode 100644 testsuite/pyunit/dom/examples/SimplePackage.vhdl diff --git a/testsuite/pyunit/SimpleEntity.vhdl b/testsuite/pyunit/SimpleEntity.vhdl deleted file mode 100644 index bdeae47e1..000000000 --- a/testsuite/pyunit/SimpleEntity.vhdl +++ /dev/null @@ -1,55 +0,0 @@ --- Author: Patrick Lehmann --- --- A generic counter module used in the StopWatch example. --- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -use work.Utilities.all; - --- Generic modulo N counter --- --- This component implements a generic modulo N counter with synchronous reset --- and enable. It generates a wrap-around strobe signal when it roles from --- MODULO-1 back to zero. --- --- .. hint:: --- --- A modulo N counter counts binary from zero to N-1. --- --- This component uses VHDL-2008 features like readback of ``out`` ports. -entity Counter is - generic ( - MODULO : positive; -- Modulo value. - BITS : natural := log2(MODULO) -- Number of expected output bits. - ); - port ( - Clock : in std_logic; -- Component clock - Reset : in std_logic; -- Component reset (synchronous) - Enable : in std_logic; -- Component enable (synchronous) - - Value : out unsigned(BITS - 1 downto 0); -- Current counter value - WrapAround : out std_logic -- Strobe output on change from MODULO-1 to zero - ); -end entity; - - --- Synthesizable and simulatable variant of a generic counter. -architecture rtl of Counter is - signal CounterValue : unsigned(log2(MODULO) - 1 downto 0) := (others => '0'); -begin - process (Clock) - begin - if rising_edge(Clock) then - if ((Reset or WrapAround) = '1') then - CounterValue <= (others => '0'); - elsif (Enable = '1') then - CounterValue <= CounterValue + 1; - end if; - end if; - end process; - - Value <= resize(CounterValue, BITS); - WrapAround <= Enable when (CounterValue = MODULO - 1) else '0'; -end architecture; diff --git a/testsuite/pyunit/SimplePackage.vhdl b/testsuite/pyunit/SimplePackage.vhdl deleted file mode 100644 index dca7e15dc..000000000 --- a/testsuite/pyunit/SimplePackage.vhdl +++ /dev/null @@ -1,15 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - --- Documentation before pack_1 -package pack_1 is - -- Global constant const_1 - constant const_1 : boolean := false; - -end package; - -package body pack_1 is - constant const_2 : boolean := true; - -end package body; diff --git a/testsuite/pyunit/dom/Simple.py b/testsuite/pyunit/dom/Simple.py new file mode 100644 index 000000000..32033609d --- /dev/null +++ b/testsuite/pyunit/dom/Simple.py @@ -0,0 +1,140 @@ +# ============================================================================= +# ____ _ _ ____ _ _ +# _ __ _ _ / ___| | | | _ \| | __| | ___ _ __ ___ +# | '_ \| | | | | _| |_| | | | | | / _` |/ _ \| '_ ` _ \ +# | |_) | |_| | |_| | _ | |_| | |___ | (_| | (_) | | | | | | +# | .__/ \__, |\____|_| |_|____/|_____(_)__,_|\___/|_| |_| |_| +# |_| |___/ +# ============================================================================= +# Authors: +# Patrick Lehmann +# +# Testsuite: Check libghdl IIR translation with a simple entity. +# +# License: +# ============================================================================ +# Copyright (C) 2019-2021 Tristan Gingold +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . +# +# SPDX-License-Identifier: GPL-2.0-or-later +# ============================================================================ +from pathlib import Path +from unittest import TestCase + +from pyGHDL.dom.NonStandard import Design, Document + + +if __name__ == "__main__": + print("ERROR: you called a testcase declaration file as an executable module.") + print("Use: 'python -m unitest '") + exit(1) + + +class SimpleEntity(TestCase): + _root = Path(__file__).resolve().parent.parent + _filename: Path = _root / "dom/examples/SimpleEntity.vhdl" + + def test_Design(self): + design = Design() + + self.assertIsNotNone(design) + + # def test_Library(self): + # library = Library() + + def test_Document(self): + design = Design() + document = Document(self._filename) + design.Documents.append(document) + + self.assertEqual(1, len(design.Documents)) + print() + print(document.Documentation) + self.assertEqual(4, len(document.Documentation.splitlines())) + + def test_Entity(self): + design = Design() + document = Document(self._filename) + design.Documents.append(document) + + self.assertEqual(1, len(design.Documents[0].Entities)) + + entity = design.Documents[0].Entities[0] + self.assertEqual("Counter", entity.Identifier) + print() + print(entity.Documentation) + self.assertEqual(11, len(entity.Documentation.splitlines())) + + def test_Architecture(self): + design = Design() + document = Document(self._filename) + design.Documents.append(document) + + self.assertEqual(1, len(design.Documents[0].Architectures)) + + architecture = design.Documents[0].Architectures[0] + self.assertEqual("rtl", architecture.Identifier) + print() + print(architecture.Documentation) + self.assertEqual(1, len(architecture.Documentation.splitlines())) + + +class SimplePackage(TestCase): + _root = Path(__file__).resolve().parent.parent + _filename: Path = _root / "dom/examples/SimplePackage.vhdl" + + def test_Design(self): + design = Design() + + self.assertIsNotNone(design) + + # def test_Library(self): + # library = Library() + + def test_Document(self): + design = Design() + document = Document(self._filename) + design.Documents.append(document) + + self.assertEqual(1, len(design.Documents)) + print() + print(document.Documentation) + self.assertEqual(4, len(document.Documentation.splitlines())) + + def test_Package(self): + design = Design() + document = Document(self._filename) + design.Documents.append(document) + + self.assertEqual(1, len(design.Documents[0].Packages)) + + package = design.Documents[0].Packages[0] + self.assertEqual("utilities", package.Identifier) + print() + print(package.Documentation) + self.assertEqual(1, len(package.Documentation.splitlines())) + + def test_PackageBody(self): + design = Design() + document = Document(self._filename) + design.Documents.append(document) + + self.assertEqual(1, len(design.Documents[0].PackageBodies)) + + packageBodies = design.Documents[0].PackageBodies[0] + self.assertEqual("utilities", packageBodies.Identifier) + print() + print(packageBodies.Documentation) + self.assertEqual(0, len(packageBodies.Documentation.splitlines())) diff --git a/testsuite/pyunit/dom/SimpleEntity.py b/testsuite/pyunit/dom/SimpleEntity.py deleted file mode 100644 index c2167c973..000000000 --- a/testsuite/pyunit/dom/SimpleEntity.py +++ /dev/null @@ -1,91 +0,0 @@ -# ============================================================================= -# ____ _ _ ____ _ _ -# _ __ _ _ / ___| | | | _ \| | __| | ___ _ __ ___ -# | '_ \| | | | | _| |_| | | | | | / _` |/ _ \| '_ ` _ \ -# | |_) | |_| | |_| | _ | |_| | |___ | (_| | (_) | | | | | | -# | .__/ \__, |\____|_| |_|____/|_____(_)__,_|\___/|_| |_| |_| -# |_| |___/ -# ============================================================================= -# Authors: -# Patrick Lehmann -# -# Testsuite: Check libghdl IIR translation with a simple entity. -# -# License: -# ============================================================================ -# Copyright (C) 2019-2021 Tristan Gingold -# -# This program is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# -# SPDX-License-Identifier: GPL-2.0-or-later -# ============================================================================ -from pathlib import Path -from unittest import TestCase - -from pyGHDL.dom.NonStandard import Design, Document - - -if __name__ == "__main__": - print("ERROR: you called a testcase declaration file as an executable module.") - print("Use: 'python -m unitest '") - exit(1) - - -class SimpleEntity(TestCase): - _root = Path(__file__).resolve().parent.parent - _filename: Path = _root / "SimpleEntity.vhdl" - - def test_Design(self): - design = Design() - - self.assertIsNotNone(design) - - # def test_Library(self): - # library = Library() - - def test_Document(self): - design = Design() - document = Document(self._filename) - design.Documents.append(document) - - self.assertEqual(1, len(design.Documents)) - print() - print(document.Documentation) - self.assertEqual(4, len(document.Documentation.splitlines())) - - def test_Entity(self): - design = Design() - document = Document(self._filename) - design.Documents.append(document) - - self.assertEqual(1, len(design.Documents[0].Entities)) - - entity = design.Documents[0].Entities[0] - self.assertEqual("Counter", entity.Identifier) - print() - print(entity.Documentation) - self.assertEqual(11, len(entity.Documentation.splitlines())) - - def test_Architecture(self): - design = Design() - document = Document(self._filename) - design.Documents.append(document) - - self.assertEqual(1, len(design.Documents[0].Architectures)) - - architecture = design.Documents[0].Architectures[0] - self.assertEqual("rtl", architecture.Identifier) - print() - print(architecture.Documentation) - self.assertEqual(1, len(architecture.Documentation.splitlines())) diff --git a/testsuite/pyunit/dom/examples/SimpleEntity.vhdl b/testsuite/pyunit/dom/examples/SimpleEntity.vhdl new file mode 100644 index 000000000..bdeae47e1 --- /dev/null +++ b/testsuite/pyunit/dom/examples/SimpleEntity.vhdl @@ -0,0 +1,55 @@ +-- Author: Patrick Lehmann +-- +-- A generic counter module used in the StopWatch example. +-- +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +use work.Utilities.all; + +-- Generic modulo N counter +-- +-- This component implements a generic modulo N counter with synchronous reset +-- and enable. It generates a wrap-around strobe signal when it roles from +-- MODULO-1 back to zero. +-- +-- .. hint:: +-- +-- A modulo N counter counts binary from zero to N-1. +-- +-- This component uses VHDL-2008 features like readback of ``out`` ports. +entity Counter is + generic ( + MODULO : positive; -- Modulo value. + BITS : natural := log2(MODULO) -- Number of expected output bits. + ); + port ( + Clock : in std_logic; -- Component clock + Reset : in std_logic; -- Component reset (synchronous) + Enable : in std_logic; -- Component enable (synchronous) + + Value : out unsigned(BITS - 1 downto 0); -- Current counter value + WrapAround : out std_logic -- Strobe output on change from MODULO-1 to zero + ); +end entity; + + +-- Synthesizable and simulatable variant of a generic counter. +architecture rtl of Counter is + signal CounterValue : unsigned(log2(MODULO) - 1 downto 0) := (others => '0'); +begin + process (Clock) + begin + if rising_edge(Clock) then + if ((Reset or WrapAround) = '1') then + CounterValue <= (others => '0'); + elsif (Enable = '1') then + CounterValue <= CounterValue + 1; + end if; + end if; + end process; + + Value <= resize(CounterValue, BITS); + WrapAround <= Enable when (CounterValue = MODULO - 1) else '0'; +end architecture; diff --git a/testsuite/pyunit/dom/examples/SimplePackage.vhdl b/testsuite/pyunit/dom/examples/SimplePackage.vhdl new file mode 100644 index 000000000..04df1c521 --- /dev/null +++ b/testsuite/pyunit/dom/examples/SimplePackage.vhdl @@ -0,0 +1,28 @@ +-- Author: Patrick Lehmann +-- +-- A collection of utility types and functions. +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- Utility package +package utilities is + -- Deferred constant to distinguish simulation from synthesis. + constant IS_SIMULATION : boolean; + +end package; + +package body utilities is + function simulation return boolean is + variable result : boolean := false; + begin + -- synthesis translate off + result := true; + -- synthesis translate on + return result; + end function; + + constant IS_SIMULATION : boolean := simulation; + +end package body; -- cgit v1.2.3