From 4c3d63af12bcd1a346696b1ce9a226f5b83456ad Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sun, 22 Aug 2021 22:16:05 +0200
Subject: testsuite/gna: add test for #1672

---
 testsuite/gna/issue1672/dut.vhdl     | 17 +++++++++++++++++
 testsuite/gna/issue1672/repro.vhdl   | 20 ++++++++++++++++++++
 testsuite/gna/issue1672/test.vhdl    | 22 ++++++++++++++++++++++
 testsuite/gna/issue1672/testsuite.sh | 15 +++++++++++++++
 4 files changed, 74 insertions(+)
 create mode 100644 testsuite/gna/issue1672/dut.vhdl
 create mode 100644 testsuite/gna/issue1672/repro.vhdl
 create mode 100644 testsuite/gna/issue1672/test.vhdl
 create mode 100755 testsuite/gna/issue1672/testsuite.sh

diff --git a/testsuite/gna/issue1672/dut.vhdl b/testsuite/gna/issue1672/dut.vhdl
new file mode 100644
index 000000000..0aaf5d28d
--- /dev/null
+++ b/testsuite/gna/issue1672/dut.vhdl
@@ -0,0 +1,17 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dut is
+  generic (
+    num_ports : integer
+  );
+  port (
+    clocks : std_logic_vector(0 to num_ports - 1)
+  );
+end entity;
+
+architecture a of dut is
+
+begin
+
+end architecture;
diff --git a/testsuite/gna/issue1672/repro.vhdl b/testsuite/gna/issue1672/repro.vhdl
new file mode 100644
index 000000000..ad4ee55ea
--- /dev/null
+++ b/testsuite/gna/issue1672/repro.vhdl
@@ -0,0 +1,20 @@
+entity repro_sub is
+  generic (num_ports : integer);
+  port (clocks : bit_vector(0 to num_ports - 1));
+end entity;
+
+architecture a of repro_sub is
+begin
+end architecture;
+
+
+entity repro is
+end entity;
+
+architecture a of repro is
+  signal clock : bit := '0';
+begin
+  repro_sub_inst : entity work.repro_sub
+    generic map (num_ports => 4)
+    port map (clocks => (others => clock));
+end architecture;
diff --git a/testsuite/gna/issue1672/test.vhdl b/testsuite/gna/issue1672/test.vhdl
new file mode 100644
index 000000000..c3fc5f13f
--- /dev/null
+++ b/testsuite/gna/issue1672/test.vhdl
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity test is
+end entity;
+
+architecture a of test is
+
+  constant num_ports : positive := 4;
+  signal clock : std_logic := '0';
+
+begin
+
+  dut_inst : entity work.dut
+    generic map (
+      num_ports => num_ports
+    )
+    port map (
+      clocks => (others => clock)
+    );
+
+end architecture;
diff --git a/testsuite/gna/issue1672/testsuite.sh b/testsuite/gna/issue1672/testsuite.sh
new file mode 100755
index 000000000..d9f957f25
--- /dev/null
+++ b/testsuite/gna/issue1672/testsuite.sh
@@ -0,0 +1,15 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze dut.vhdl
+analyze test.vhdl
+elab_simulate test
+
+analyze repro.vhdl
+elab_simulate repro
+
+clean
+
+echo "Test successful"
-- 
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