From 43ee1ba79a5d7753701b20b294f9f379e45c1b96 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Tue, 26 Nov 2019 19:35:48 +0100 Subject: vhdl: recognize sin and cos from math_real. --- python/libghdl/thin/std_names.py | 358 +++++++++++++++++++------------------- python/libghdl/thin/vhdl/nodes.py | 96 +++++----- src/std_names.adb | 2 + src/std_names.ads | 4 +- src/vhdl/vhdl-ieee-math_real.adb | 4 + src/vhdl/vhdl-nodes.ads | 2 + 6 files changed, 240 insertions(+), 226 deletions(-) diff --git a/python/libghdl/thin/std_names.py b/python/libghdl/thin/std_names.py index 5d6e028ba..27639788f 100644 --- a/python/libghdl/thin/std_names.py +++ b/python/libghdl/thin/std_names.py @@ -598,181 +598,183 @@ class Name: Math_Real = 812 Ceil = 813 Log2 = 814 - Last_Ieee = 814 - First_Synthesis = 815 - Allconst = 815 - Allseq = 816 - Anyconst = 817 - Anyseq = 818 - Last_Synthesis = 818 - First_Directive = 819 - Define = 819 - Endif = 820 - Ifdef = 821 - Ifndef = 822 - Include = 823 - Timescale = 824 - Undef = 825 - Protect = 826 - Begin_Protected = 827 - End_Protected = 828 - Key_Block = 829 - Data_Block = 830 - Line = 831 - Celldefine = 832 - Endcelldefine = 833 - Default_Nettype = 834 - Resetall = 835 - Last_Directive = 835 - First_Systask = 836 - Bits = 836 - D_Root = 837 - D_Unit = 838 - Last_Systask = 838 - First_SV_Method = 839 - Size = 839 - Insert = 840 - Delete = 841 - Pop_Front = 842 - Pop_Back = 843 - Push_Front = 844 - Push_Back = 845 - Name = 846 - Len = 847 - Substr = 848 - Exists = 849 - Atoi = 850 - Itoa = 851 - Find = 852 - Find_Index = 853 - Find_First = 854 - Find_First_Index = 855 - Find_Last = 856 - Find_Last_Index = 857 - Num = 858 - Randomize = 859 - Pre_Randomize = 860 - Post_Randomize = 861 - Srandom = 862 - Get_Randstate = 863 - Set_Randstate = 864 - Seed = 865 - State = 866 - Last_SV_Method = 866 - First_BSV = 867 - uAction = 867 - uActionValue = 868 - BVI = 869 - uC = 870 - uCF = 871 - uE = 872 - uSB = 873 - uSBR = 874 - Action = 875 - Endaction = 876 - Actionvalue = 877 - Endactionvalue = 878 - Ancestor = 879 - Clocked_By = 880 - Default_Clock = 881 - Default_Reset = 882 - Dependencies = 883 - Deriving = 884 - Determines = 885 - Enable = 886 - Ifc_Inout = 887 - Input_Clock = 888 - Input_Reset = 889 - Instance = 890 - Endinstance = 891 - Let = 892 - Match = 893 - Method = 894 - Endmethod = 895 - Numeric = 896 - Output_Clock = 897 - Output_Reset = 898 - Par = 899 - Endpar = 900 - Path = 901 - Provisos = 902 - Ready = 903 - Reset_By = 904 - Rule = 905 - Endrule = 906 - Rules = 907 - Endrules = 908 - Same_Family = 909 - Schedule = 910 - Seq = 911 - Endseq = 912 - Typeclass = 913 - Endtypeclass = 914 - Valueof = 915 - uValueof = 916 - Last_BSV = 916 - First_Comment = 917 - Psl = 917 - Pragma = 918 - Synthesis = 919 - Synopsys = 920 - Translate_Off = 921 - Translate_On = 922 - Last_Comment = 922 - First_PSL = 923 - A = 923 - Af = 924 - Ag = 925 - Ax = 926 - Abort = 927 - Assume_Guarantee = 928 - Before = 929 - Clock = 930 - E = 931 - Ef = 932 - Eg = 933 - Ex = 934 - Endpoint = 935 - Eventually = 936 - Fairness = 937 - Fell = 938 - Forall = 939 - G = 940 - Inf = 941 - Inherit = 942 - Never = 943 - Next_A = 944 - Next_E = 945 - Next_Event = 946 - Next_Event_A = 947 - Next_Event_E = 948 - Prev = 949 - Rose = 950 - Strong = 951 - W = 952 - Whilenot = 953 - Within = 954 - X = 955 - Last_PSL = 955 - First_Edif = 956 - Celltype = 966 - View = 967 - Viewtype = 968 - Direction = 969 - Contents = 970 - Net = 971 - Viewref = 972 - Cellref = 973 - Libraryref = 974 - Portinstance = 975 - Joined = 976 - Portref = 977 - Instanceref = 978 - Design = 979 - Designator = 980 - Owner = 981 - Member = 982 - Number = 983 - Rename = 984 - Userdata = 985 - Last_Edif = 985 + Sin = 815 + Cos = 816 + Last_Ieee = 816 + First_Synthesis = 817 + Allconst = 817 + Allseq = 818 + Anyconst = 819 + Anyseq = 820 + Last_Synthesis = 820 + First_Directive = 821 + Define = 821 + Endif = 822 + Ifdef = 823 + Ifndef = 824 + Include = 825 + Timescale = 826 + Undef = 827 + Protect = 828 + Begin_Protected = 829 + End_Protected = 830 + Key_Block = 831 + Data_Block = 832 + Line = 833 + Celldefine = 834 + Endcelldefine = 835 + Default_Nettype = 836 + Resetall = 837 + Last_Directive = 837 + First_Systask = 838 + Bits = 838 + D_Root = 839 + D_Unit = 840 + Last_Systask = 840 + First_SV_Method = 841 + Size = 841 + Insert = 842 + Delete = 843 + Pop_Front = 844 + Pop_Back = 845 + Push_Front = 846 + Push_Back = 847 + Name = 848 + Len = 849 + Substr = 850 + Exists = 851 + Atoi = 852 + Itoa = 853 + Find = 854 + Find_Index = 855 + Find_First = 856 + Find_First_Index = 857 + Find_Last = 858 + Find_Last_Index = 859 + Num = 860 + Randomize = 861 + Pre_Randomize = 862 + Post_Randomize = 863 + Srandom = 864 + Get_Randstate = 865 + Set_Randstate = 866 + Seed = 867 + State = 868 + Last_SV_Method = 868 + First_BSV = 869 + uAction = 869 + uActionValue = 870 + BVI = 871 + uC = 872 + uCF = 873 + uE = 874 + uSB = 875 + uSBR = 876 + Action = 877 + Endaction = 878 + Actionvalue = 879 + Endactionvalue = 880 + Ancestor = 881 + Clocked_By = 882 + Default_Clock = 883 + Default_Reset = 884 + Dependencies = 885 + Deriving = 886 + Determines = 887 + Enable = 888 + Ifc_Inout = 889 + Input_Clock = 890 + Input_Reset = 891 + Instance = 892 + Endinstance = 893 + Let = 894 + Match = 895 + Method = 896 + Endmethod = 897 + Numeric = 898 + Output_Clock = 899 + Output_Reset = 900 + Par = 901 + Endpar = 902 + Path = 903 + Provisos = 904 + Ready = 905 + Reset_By = 906 + Rule = 907 + Endrule = 908 + Rules = 909 + Endrules = 910 + Same_Family = 911 + Schedule = 912 + Seq = 913 + Endseq = 914 + Typeclass = 915 + Endtypeclass = 916 + Valueof = 917 + uValueof = 918 + Last_BSV = 918 + First_Comment = 919 + Psl = 919 + Pragma = 920 + Synthesis = 921 + Synopsys = 922 + Translate_Off = 923 + Translate_On = 924 + Last_Comment = 924 + First_PSL = 925 + A = 925 + Af = 926 + Ag = 927 + Ax = 928 + Abort = 929 + Assume_Guarantee = 930 + Before = 931 + Clock = 932 + E = 933 + Ef = 934 + Eg = 935 + Ex = 936 + Endpoint = 937 + Eventually = 938 + Fairness = 939 + Fell = 940 + Forall = 941 + G = 942 + Inf = 943 + Inherit = 944 + Never = 945 + Next_A = 946 + Next_E = 947 + Next_Event = 948 + Next_Event_A = 949 + Next_Event_E = 950 + Prev = 951 + Rose = 952 + Strong = 953 + W = 954 + Whilenot = 955 + Within = 956 + X = 957 + Last_PSL = 957 + First_Edif = 958 + Celltype = 968 + View = 969 + Viewtype = 970 + Direction = 971 + Contents = 972 + Net = 973 + Viewref = 974 + Cellref = 975 + Libraryref = 976 + Portinstance = 977 + Joined = 978 + Portref = 979 + Instanceref = 980 + Design = 981 + Designator = 982 + Owner = 983 + Member = 984 + Number = 985 + Rename = 986 + Userdata = 987 + Last_Edif = 987 diff --git a/python/libghdl/thin/vhdl/nodes.py b/python/libghdl/thin/vhdl/nodes.py index 57ea761ab..15b1d9074 100644 --- a/python/libghdl/thin/vhdl/nodes.py +++ b/python/libghdl/thin/vhdl/nodes.py @@ -1176,53 +1176,55 @@ class Iir_Predefined: Ieee_Numeric_Std_Match_Suv = 297 Ieee_Math_Real_Ceil = 298 Ieee_Math_Real_Log2 = 299 - Ieee_Std_Logic_Unsigned_Add_Slv_Slv = 300 - Ieee_Std_Logic_Unsigned_Add_Slv_Int = 301 - Ieee_Std_Logic_Unsigned_Add_Int_Slv = 302 - Ieee_Std_Logic_Unsigned_Add_Slv_Sl = 303 - Ieee_Std_Logic_Unsigned_Add_Sl_Slv = 304 - Ieee_Std_Logic_Unsigned_Sub_Slv_Slv = 305 - Ieee_Std_Logic_Unsigned_Sub_Slv_Int = 306 - Ieee_Std_Logic_Unsigned_Sub_Int_Slv = 307 - Ieee_Std_Logic_Unsigned_Sub_Slv_Sl = 308 - Ieee_Std_Logic_Unsigned_Sub_Sl_Slv = 309 - Ieee_Std_Logic_Unsigned_Lt_Slv_Slv = 310 - Ieee_Std_Logic_Unsigned_Lt_Slv_Int = 311 - Ieee_Std_Logic_Unsigned_Lt_Int_Slv = 312 - Ieee_Std_Logic_Unsigned_Le_Slv_Slv = 313 - Ieee_Std_Logic_Unsigned_Le_Slv_Int = 314 - Ieee_Std_Logic_Unsigned_Le_Int_Slv = 315 - Ieee_Std_Logic_Unsigned_Gt_Slv_Slv = 316 - Ieee_Std_Logic_Unsigned_Gt_Slv_Int = 317 - Ieee_Std_Logic_Unsigned_Gt_Int_Slv = 318 - Ieee_Std_Logic_Unsigned_Ge_Slv_Slv = 319 - Ieee_Std_Logic_Unsigned_Ge_Slv_Int = 320 - Ieee_Std_Logic_Unsigned_Ge_Int_Slv = 321 - Ieee_Std_Logic_Unsigned_Eq_Slv_Slv = 322 - Ieee_Std_Logic_Unsigned_Eq_Slv_Int = 323 - Ieee_Std_Logic_Unsigned_Eq_Int_Slv = 324 - Ieee_Std_Logic_Unsigned_Ne_Slv_Slv = 325 - Ieee_Std_Logic_Unsigned_Ne_Slv_Int = 326 - Ieee_Std_Logic_Unsigned_Ne_Int_Slv = 327 - Ieee_Std_Logic_Unsigned_Conv_Integer = 328 - Ieee_Std_Logic_Signed_Add_Slv_Slv = 329 - Ieee_Std_Logic_Signed_Add_Slv_Int = 330 - Ieee_Std_Logic_Signed_Add_Int_Slv = 331 - Ieee_Std_Logic_Signed_Add_Slv_Sl = 332 - Ieee_Std_Logic_Signed_Add_Sl_Slv = 333 - Ieee_Std_Logic_Signed_Sub_Slv_Slv = 334 - Ieee_Std_Logic_Signed_Sub_Slv_Int = 335 - Ieee_Std_Logic_Signed_Sub_Int_Slv = 336 - Ieee_Std_Logic_Signed_Sub_Slv_Sl = 337 - Ieee_Std_Logic_Signed_Sub_Sl_Slv = 338 - Ieee_Std_Logic_Arith_Conv_Unsigned_Int = 339 - Ieee_Std_Logic_Arith_Conv_Unsigned_Uns = 340 - Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn = 341 - Ieee_Std_Logic_Arith_Conv_Unsigned_Log = 342 - Ieee_Std_Logic_Arith_Conv_Integer_Int = 343 - Ieee_Std_Logic_Arith_Conv_Integer_Uns = 344 - Ieee_Std_Logic_Arith_Conv_Integer_Sgn = 345 - Ieee_Std_Logic_Arith_Conv_Integer_Log = 346 + Ieee_Math_Real_Sin = 300 + Ieee_Math_Real_Cos = 301 + Ieee_Std_Logic_Unsigned_Add_Slv_Slv = 302 + Ieee_Std_Logic_Unsigned_Add_Slv_Int = 303 + Ieee_Std_Logic_Unsigned_Add_Int_Slv = 304 + Ieee_Std_Logic_Unsigned_Add_Slv_Sl = 305 + Ieee_Std_Logic_Unsigned_Add_Sl_Slv = 306 + Ieee_Std_Logic_Unsigned_Sub_Slv_Slv = 307 + Ieee_Std_Logic_Unsigned_Sub_Slv_Int = 308 + Ieee_Std_Logic_Unsigned_Sub_Int_Slv = 309 + Ieee_Std_Logic_Unsigned_Sub_Slv_Sl = 310 + Ieee_Std_Logic_Unsigned_Sub_Sl_Slv = 311 + Ieee_Std_Logic_Unsigned_Lt_Slv_Slv = 312 + Ieee_Std_Logic_Unsigned_Lt_Slv_Int = 313 + Ieee_Std_Logic_Unsigned_Lt_Int_Slv = 314 + Ieee_Std_Logic_Unsigned_Le_Slv_Slv = 315 + Ieee_Std_Logic_Unsigned_Le_Slv_Int = 316 + Ieee_Std_Logic_Unsigned_Le_Int_Slv = 317 + Ieee_Std_Logic_Unsigned_Gt_Slv_Slv = 318 + Ieee_Std_Logic_Unsigned_Gt_Slv_Int = 319 + Ieee_Std_Logic_Unsigned_Gt_Int_Slv = 320 + Ieee_Std_Logic_Unsigned_Ge_Slv_Slv = 321 + Ieee_Std_Logic_Unsigned_Ge_Slv_Int = 322 + Ieee_Std_Logic_Unsigned_Ge_Int_Slv = 323 + Ieee_Std_Logic_Unsigned_Eq_Slv_Slv = 324 + Ieee_Std_Logic_Unsigned_Eq_Slv_Int = 325 + Ieee_Std_Logic_Unsigned_Eq_Int_Slv = 326 + Ieee_Std_Logic_Unsigned_Ne_Slv_Slv = 327 + Ieee_Std_Logic_Unsigned_Ne_Slv_Int = 328 + Ieee_Std_Logic_Unsigned_Ne_Int_Slv = 329 + Ieee_Std_Logic_Unsigned_Conv_Integer = 330 + Ieee_Std_Logic_Signed_Add_Slv_Slv = 331 + Ieee_Std_Logic_Signed_Add_Slv_Int = 332 + Ieee_Std_Logic_Signed_Add_Int_Slv = 333 + Ieee_Std_Logic_Signed_Add_Slv_Sl = 334 + Ieee_Std_Logic_Signed_Add_Sl_Slv = 335 + Ieee_Std_Logic_Signed_Sub_Slv_Slv = 336 + Ieee_Std_Logic_Signed_Sub_Slv_Int = 337 + Ieee_Std_Logic_Signed_Sub_Int_Slv = 338 + Ieee_Std_Logic_Signed_Sub_Slv_Sl = 339 + Ieee_Std_Logic_Signed_Sub_Sl_Slv = 340 + Ieee_Std_Logic_Arith_Conv_Unsigned_Int = 341 + Ieee_Std_Logic_Arith_Conv_Unsigned_Uns = 342 + Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn = 343 + Ieee_Std_Logic_Arith_Conv_Unsigned_Log = 344 + Ieee_Std_Logic_Arith_Conv_Integer_Int = 345 + Ieee_Std_Logic_Arith_Conv_Integer_Uns = 346 + Ieee_Std_Logic_Arith_Conv_Integer_Sgn = 347 + Ieee_Std_Logic_Arith_Conv_Integer_Log = 348 Get_Kind = libghdl.vhdl__nodes__get_kind Get_Location = libghdl.vhdl__nodes__get_location diff --git a/src/std_names.adb b/src/std_names.adb index ff53371f0..5612363d4 100644 --- a/src/std_names.adb +++ b/src/std_names.adb @@ -650,6 +650,8 @@ package body Std_Names is Def ("math_real", Name_Math_Real); Def ("ceil", Name_Ceil); Def ("log2", Name_Log2); + Def ("sin", Name_Sin); + Def ("cos", Name_Cos); Def ("allconst", Name_Allconst); Def ("allseq", Name_Allseq); diff --git a/src/std_names.ads b/src/std_names.ads index 1b0d8b094..57901576b 100644 --- a/src/std_names.ads +++ b/src/std_names.ads @@ -731,7 +731,9 @@ package Std_Names is Name_Math_Real : constant Name_Id := Name_First_Ieee + 032; Name_Ceil : constant Name_Id := Name_First_Ieee + 033; Name_Log2 : constant Name_Id := Name_First_Ieee + 034; - Name_Last_Ieee : constant Name_Id := Name_Log2; + Name_Sin : constant Name_Id := Name_First_Ieee + 035; + Name_Cos : constant Name_Id := Name_First_Ieee + 036; + Name_Last_Ieee : constant Name_Id := Name_Cos; Name_First_Synthesis : constant Name_Id := Name_Last_Ieee + 1; Name_Allconst : constant Name_Id := Name_First_Synthesis + 000; diff --git a/src/vhdl/vhdl-ieee-math_real.adb b/src/vhdl/vhdl-ieee-math_real.adb index d62e4c246..1ac5a9b10 100644 --- a/src/vhdl/vhdl-ieee-math_real.adb +++ b/src/vhdl/vhdl-ieee-math_real.adb @@ -44,6 +44,10 @@ package body Vhdl.Ieee.Math_Real is Predef := Iir_Predefined_Ieee_Math_Real_Ceil; when Name_Log2 => Predef := Iir_Predefined_Ieee_Math_Real_Log2; + when Name_Sin => + Predef := Iir_Predefined_Ieee_Math_Real_Sin; + when Name_Cos => + Predef := Iir_Predefined_Ieee_Math_Real_Cos; when others => null; end case; diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 10ad3d853..1f65efb0f 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -5065,6 +5065,8 @@ package Vhdl.Nodes is -- Math_Real Iir_Predefined_Ieee_Math_Real_Ceil, Iir_Predefined_Ieee_Math_Real_Log2, + Iir_Predefined_Ieee_Math_Real_Sin, + Iir_Predefined_Ieee_Math_Real_Cos, -- Std_Logic_Unsigned (synopsys extension). Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Slv, -- cgit v1.2.3