From 3dcf90fdee4286d5852604df417a5b6e75382265 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Mon, 29 Jul 2019 19:40:29 +0200
Subject: synth: add a test for psl.

---
 testsuite/synth/psl01/hello.vhdl   | 28 ++++++++++++++++++++++++++++
 testsuite/synth/psl01/testsuite.sh | 10 ++++++++++
 2 files changed, 38 insertions(+)
 create mode 100644 testsuite/synth/psl01/hello.vhdl
 create mode 100755 testsuite/synth/psl01/testsuite.sh

diff --git a/testsuite/synth/psl01/hello.vhdl b/testsuite/synth/psl01/hello.vhdl
new file mode 100644
index 000000000..fcf517757
--- /dev/null
+++ b/testsuite/synth/psl01/hello.vhdl
@@ -0,0 +1,28 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity hello is
+ port (clk, rst: std_logic;
+       cnt : out unsigned(3 downto 0));
+end hello;
+
+architecture behav of hello is
+ signal val : unsigned (3 downto 0);
+begin
+ process(clk)
+ begin
+   if rising_edge(clk) then
+     if rst = '1' then
+       val <= (others => '0');
+     else
+       val <= val + 1;
+     end if;
+   end if;
+ end process;
+ cnt <= val;
+
+ --psl default clock is clk;
+ --psl restrict {rst; (not rst)[*]};
+ assert val /= 5 or rst = '1' severity error;
+end behav;
diff --git a/testsuite/synth/psl01/testsuite.sh b/testsuite/synth/psl01/testsuite.sh
new file mode 100755
index 000000000..e6d4050e6
--- /dev/null
+++ b/testsuite/synth/psl01/testsuite.sh
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+synth -fpsl hello.vhdl -e hello > syn_hello.vhdl
+analyze syn_hello.vhdl
+clean
+
+echo "Test successful"
-- 
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