From 334e6277a5ac7a0f04c26a3b274ab8db7b7020a7 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sat, 26 Oct 2019 08:28:27 +0200
Subject: testsuite/synth/psl02: renaming.

---
 testsuite/synth/psl02/verif3.vhdl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/testsuite/synth/psl02/verif3.vhdl b/testsuite/synth/psl02/verif3.vhdl
index c1b262177..abc5ad220 100644
--- a/testsuite/synth/psl02/verif3.vhdl
+++ b/testsuite/synth/psl02/verif3.vhdl
@@ -1,4 +1,4 @@
-vunit verif2 (assert2(behav))
+vunit verif3 (assert2(behav))
 {
   default clock is rising_edge(clk);
   assume always val < 10;
-- 
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