From 2fbafb8b74e6eb8f1f6a0ff5d5a113f9ca0645b7 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Wed, 25 Aug 2021 07:44:14 +0200
Subject: testsuite/gna: add a testcase for #1844

---
 testsuite/gna/issue1844/repro1.vhdl  | 45 ++++++++++++++++++++++++++++++++++++
 testsuite/gna/issue1844/testsuite.sh | 11 +++++++++
 2 files changed, 56 insertions(+)
 create mode 100644 testsuite/gna/issue1844/repro1.vhdl
 create mode 100755 testsuite/gna/issue1844/testsuite.sh

diff --git a/testsuite/gna/issue1844/repro1.vhdl b/testsuite/gna/issue1844/repro1.vhdl
new file mode 100644
index 000000000..cf2ea6328
--- /dev/null
+++ b/testsuite/gna/issue1844/repro1.vhdl
@@ -0,0 +1,45 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+package utils is
+  type slv_array is array(natural range <>) of std_logic_vector;
+
+  function slv_or (vv: slv_array) return std_logic_vector;
+end utils;
+
+package body utils is
+--  function slv_or is (vv: slv_array) return std_logic_vector
+  function slv_or (vv: slv_array) return std_logic_vector
+  is
+    variable res : std_logic_vector(vv (vv'left)'range);
+  begin
+    res := (others => '0');
+    for i in vv'range loop
+      res := res or vv (i);
+    end loop;
+    return res;
+  end slv_or;
+end utils;
+
+
+entity repro1 is
+end;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.utils.all;
+
+architecture behav of repro1 is
+begin
+  process
+    constant c : slv_array := (x"01", x"e0");
+    variable v : std_logic_vector(7 downto 0);
+  begin
+    v := slv_or (c);
+    assert v = x"e1" severity failure;
+    wait;
+  end process;
+end;
+
+
diff --git a/testsuite/gna/issue1844/testsuite.sh b/testsuite/gna/issue1844/testsuite.sh
new file mode 100755
index 000000000..507958a4d
--- /dev/null
+++ b/testsuite/gna/issue1844/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze repro1.vhdl
+elab_simulate repro1
+
+clean
+
+echo "Test successful"
-- 
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