From 2efaa2396acf02fecc75341eb88353a325290e0b Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Fri, 27 Jan 2023 22:08:39 +0100 Subject: testsuite/synth: add tests for #2327 --- testsuite/synth/issue2327/tb_test_tf.vhdl | 72 +++++++++++++++++++++++++++++++ testsuite/synth/issue2327/test_and.vhdl | 11 +++++ testsuite/synth/issue2327/test_tf.vhdl | 38 ++++++++++++++++ testsuite/synth/issue2327/testsuite.sh | 11 +++++ 4 files changed, 132 insertions(+) create mode 100644 testsuite/synth/issue2327/tb_test_tf.vhdl create mode 100644 testsuite/synth/issue2327/test_and.vhdl create mode 100644 testsuite/synth/issue2327/test_tf.vhdl create mode 100755 testsuite/synth/issue2327/testsuite.sh diff --git a/testsuite/synth/issue2327/tb_test_tf.vhdl b/testsuite/synth/issue2327/tb_test_tf.vhdl new file mode 100644 index 000000000..0ff4dc7d7 --- /dev/null +++ b/testsuite/synth/issue2327/tb_test_tf.vhdl @@ -0,0 +1,72 @@ +entity tb_test_tf is +end tb_test_tf; + +architecture behav of tb_test_tf is + signal a : bit_vector(7 downto 0); + signal e : bit; + signal ea_and : bit_vector(7 downto 0); + signal ae_and : bit_vector(7 downto 0); + signal ea_nand : bit_vector(7 downto 0); + signal ae_nand : bit_vector(7 downto 0); + signal ea_or : bit_vector(7 downto 0); + signal ae_or : bit_vector(7 downto 0); + signal ea_nor : bit_vector(7 downto 0); + signal ae_nor : bit_vector(7 downto 0); + signal ea_xor : bit_vector(7 downto 0); + signal ae_xor : bit_vector(7 downto 0); + signal ea_xnor : bit_vector(7 downto 0); + signal ae_xnor : bit_vector(7 downto 0); +begin + dut: entity work.test_tf + port map ( + a => a, + e => e, + ea_and => ea_and, + ae_and => ae_and, + ea_nand => ea_nand, + ae_nand => ae_nand, + ea_or => ea_or, + ae_or => ae_or, + ea_nor => ea_nor, + ae_nor => ae_nor, + ea_xor => ea_xor, + ae_xor => ae_xor, + ea_xnor => ea_xnor, + ae_xnor => ae_xnor); + process + begin + a <= b"01000111"; + e <= '1'; + wait for 1 ns; + + assert ea_and = b"01000111" severity failure; + assert ae_and = b"01000111" severity failure; + assert ea_nand = b"10111000" severity failure; + assert ae_nand = b"10111000" severity failure; + assert ea_or = b"11111111" severity failure; + assert ae_or = b"11111111" severity failure; + assert ea_nor = b"00000000" severity failure; + assert ae_nor = b"00000000" severity failure; + assert ea_xor = b"10111000" severity failure; + assert ae_xor = b"10111000" severity failure; + assert ea_xnor = b"01000111" severity failure; + assert ae_xnor = b"01000111" severity failure; + + e <= '0'; + wait for 1 ns; + + assert ea_and = b"00000000" severity failure; + assert ae_and = b"00000000" severity failure; + assert ea_nand = b"11111111" severity failure; + assert ae_nand = b"11111111" severity failure; + assert ea_or = b"01000111" severity failure; + assert ae_or = b"01000111" severity failure; + assert ea_nor = b"10111000" severity failure; + assert ae_nor = b"10111000" severity failure; + assert ea_xor = b"01000111" severity failure; + assert ae_xor = b"01000111" severity failure; + assert ea_xnor = b"10111000" severity failure; + assert ae_xnor = b"10111000" severity failure; + wait; + end process; +end behav; diff --git a/testsuite/synth/issue2327/test_and.vhdl b/testsuite/synth/issue2327/test_and.vhdl new file mode 100644 index 000000000..e6bd17449 --- /dev/null +++ b/testsuite/synth/issue2327/test_and.vhdl @@ -0,0 +1,11 @@ +entity test is + port( + a: in bit_vector(7 downto 0); + b: in bit; + c: out bit_vector(7 downto 0)); +end test; + +architecture behavior of test is +begin + c <= a and b; +end behavior; diff --git a/testsuite/synth/issue2327/test_tf.vhdl b/testsuite/synth/issue2327/test_tf.vhdl new file mode 100644 index 000000000..00d16c41b --- /dev/null +++ b/testsuite/synth/issue2327/test_tf.vhdl @@ -0,0 +1,38 @@ +entity test_tf is + port( + a: in bit_vector(7 downto 0); + e: in bit; + ea_and: out bit_vector(7 downto 0); + ae_and: out bit_vector(7 downto 0); + ea_nand: out bit_vector(7 downto 0); + ae_nand: out bit_vector(7 downto 0); + ea_or: out bit_vector(7 downto 0); + ae_or: out bit_vector(7 downto 0); + ea_nor: out bit_vector(7 downto 0); + ae_nor: out bit_vector(7 downto 0); + ea_xor: out bit_vector(7 downto 0); + ae_xor: out bit_vector(7 downto 0); + ea_xnor: out bit_vector(7 downto 0); + ae_xnor: out bit_vector(7 downto 0)); +end test_tf; + +architecture behavior of test_tf is +begin + ea_and <= a and e; + ae_and <= e and a; + + ea_nand <= a nand e; + ae_nand <= e nand a; + + ea_or <= a or e; + ae_or <= e or a; + + ea_nor <= a nor e; + ae_nor <= e nor a; + + ea_xor <= a xor e; + ae_xor <= e xor a; + + ea_xnor <= a xnor e; + ae_xnor <= e xnor a; +end behavior; diff --git a/testsuite/synth/issue2327/testsuite.sh b/testsuite/synth/issue2327/testsuite.sh new file mode 100755 index 000000000..830576843 --- /dev/null +++ b/testsuite/synth/issue2327/testsuite.sh @@ -0,0 +1,11 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=--std=08 + +synth_only test_and + +synth_tb test_tf + +echo "Test successful" -- cgit v1.2.3