From 2d3991ff1b325d556ac922c679ffaf39bcdb6815 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Wed, 7 Apr 2021 21:37:10 +0200
Subject: testsuite/gna: add a test for #1715

---
 testsuite/gna/issue1715/mwe-repro.vhdl | 25 +++++++++++++++++++
 testsuite/gna/issue1715/mwe.vhdl       | 44 ++++++++++++++++++++++++++++++++++
 testsuite/gna/issue1715/testsuite.sh   | 11 +++++++++
 3 files changed, 80 insertions(+)
 create mode 100644 testsuite/gna/issue1715/mwe-repro.vhdl
 create mode 100644 testsuite/gna/issue1715/mwe.vhdl
 create mode 100755 testsuite/gna/issue1715/testsuite.sh

diff --git a/testsuite/gna/issue1715/mwe-repro.vhdl b/testsuite/gna/issue1715/mwe-repro.vhdl
new file mode 100644
index 000000000..5845538c4
--- /dev/null
+++ b/testsuite/gna/issue1715/mwe-repro.vhdl
@@ -0,0 +1,25 @@
+entity comp1 is
+  port (
+    a_i  : in bit_vector(3 downto 0)
+  );
+end entity;
+
+architecture arch of comp1 is
+begin
+end arch;
+
+entity mwe is
+end entity;
+
+architecture arch of mwe is
+  signal clk : bit := '0';
+  signal a   : bit_vector(3 downto 0);
+begin
+  process
+  begin
+    wait until clk'stable;
+  end process;
+
+  x_comp1 : entity work.comp1
+    port map (a_i  => a or a);
+end arch;
diff --git a/testsuite/gna/issue1715/mwe.vhdl b/testsuite/gna/issue1715/mwe.vhdl
new file mode 100644
index 000000000..252b05350
--- /dev/null
+++ b/testsuite/gna/issue1715/mwe.vhdl
@@ -0,0 +1,44 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity comp1 is
+  port (
+    a_i  : in std_logic_vector(3 downto 0);
+    x_o : out std_logic
+  );
+end entity;
+
+architecture arch of comp1 is
+begin
+  x_o <= a_i(0) and a_i(1) after 5 ns;
+end arch;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity mwe is
+end entity;
+
+architecture arch of mwe is
+  signal clk : std_logic := '0';
+  signal a   : std_logic_vector(3 downto 0);
+  signal x   : std_logic;
+begin
+
+  process
+  begin
+    a <= "1100";
+    wait for 10 us;
+    a <= "1011";
+
+    wait until clk'stable;
+  end process;
+
+  x_comp1 : entity work.comp1
+  port map (
+    a_i  => std_logic_vector'(a), -- this crashes if 'wait until clk'stable' isn't commented out
+  --  a_i  => a, -- this works
+    x_o  => x
+  );
+
+end arch;
diff --git a/testsuite/gna/issue1715/testsuite.sh b/testsuite/gna/issue1715/testsuite.sh
new file mode 100755
index 000000000..4ade39fc0
--- /dev/null
+++ b/testsuite/gna/issue1715/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze mwe.vhdl
+elab_simulate mwe
+
+clean
+
+echo "Test successful"
-- 
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