From 2d34c88b80275b5812ac62a3bf83354c41494265 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sun, 23 Apr 2023 08:58:30 +0200
Subject: testsuite/gna: add a test for #2421

---
 testsuite/gna/issue2421/testsuite.sh | 19 +++++++++++++++++++
 testsuite/gna/issue2421/top.vhdl     | 31 +++++++++++++++++++++++++++++++
 2 files changed, 50 insertions(+)
 create mode 100755 testsuite/gna/issue2421/testsuite.sh
 create mode 100644 testsuite/gna/issue2421/top.vhdl

diff --git a/testsuite/gna/issue2421/testsuite.sh b/testsuite/gna/issue2421/testsuite.sh
new file mode 100755
index 000000000..c6f7f1765
--- /dev/null
+++ b/testsuite/gna/issue2421/testsuite.sh
@@ -0,0 +1,19 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze_failure --std=93 top.vhdl
+analyze_failure --std=08 top.vhdl
+
+analyze top.vhdl
+elab_simulate top
+
+clean
+
+GHDL_STD_FLAGS="--std=08 -frelaxed"
+analyze top.vhdl
+elab_simulate top
+
+clean
+
+echo "Test successful"
diff --git a/testsuite/gna/issue2421/top.vhdl b/testsuite/gna/issue2421/top.vhdl
new file mode 100644
index 000000000..676e57efd
--- /dev/null
+++ b/testsuite/gna/issue2421/top.vhdl
@@ -0,0 +1,31 @@
+library ieee;
+use     ieee.std_logic_1164.all;
+
+entity comp is
+	port (
+		output : out std_logic_vector
+	);
+end entity;
+
+architecture a1 of comp is
+begin
+	output <= (others => '0');
+	-- output <= (output'range => '0');  -- gives no error
+end architecture;
+
+
+library ieee;
+use     ieee.std_logic_1164.all;
+use     ieee.numeric_std.all;
+
+entity top is
+end entity;
+
+architecture a2 of top is
+	signal sig : std_logic_vector(7 downto 0);
+begin
+	inst : entity work.comp
+		port map (
+			output => sig
+		);
+end architecture;
-- 
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