From 27656301fac956c7ca558feac3a5037c368d553b Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sat, 21 Sep 2019 16:37:35 +0200
Subject: testsuite/synth: add testcase for previous commit.

---
 testsuite/synth/bug01/display.vhdl  | 35 +++++++++++++++++++++++++++++++++++
 testsuite/synth/bug01/display2.vhdl | 35 +++++++++++++++++++++++++++++++++++
 testsuite/synth/bug01/testsuite.sh  |  9 +++++++++
 3 files changed, 79 insertions(+)
 create mode 100644 testsuite/synth/bug01/display.vhdl
 create mode 100644 testsuite/synth/bug01/display2.vhdl
 create mode 100755 testsuite/synth/bug01/testsuite.sh

diff --git a/testsuite/synth/bug01/display.vhdl b/testsuite/synth/bug01/display.vhdl
new file mode 100644
index 000000000..9059f81f4
--- /dev/null
+++ b/testsuite/synth/bug01/display.vhdl
@@ -0,0 +1,35 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity display is
+  port (
+    clk : in std_logic;
+    rst_n : in std_logic;
+    column : integer;
+    row : integer;
+    col2x : out unsigned(9 downto 0);
+    row2x : out unsigned(9 downto 0);
+    twochars : in std_logic_vector(15 downto 0)
+  );
+end display;
+
+architecture behavior of display is
+  signal disp_ena : std_logic;
+  signal ucol : unsigned(9 downto 0);
+  signal urow : unsigned(9 downto 0);
+  signal tileaddress : std_logic_vector(10 downto 0);
+  signal char : std_logic_vector(7 downto 0);
+  signal char_row : std_logic_vector(7 downto 0);
+
+begin
+
+  -- 8x8 bitmap is upscaled 2x
+  ucol <= to_unsigned(column, 10);
+  urow <= to_unsigned(row, 10);
+  col2x <= shift_right(urow, 1);
+  row2x <= shift_right(ucol, 1);
+
+
+end;
+ 
diff --git a/testsuite/synth/bug01/display2.vhdl b/testsuite/synth/bug01/display2.vhdl
new file mode 100644
index 000000000..8d7462c24
--- /dev/null
+++ b/testsuite/synth/bug01/display2.vhdl
@@ -0,0 +1,35 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity display is
+  port (
+    clk : in std_logic;
+    rst_n : in std_logic;
+    twochars : in std_logic_vector(15 downto 0)
+  );
+end display;
+
+architecture behavior of display is
+  signal disp_ena : std_logic;
+  signal column : integer;
+  signal row : integer;
+  signal col2x : unsigned(9 downto 0);
+  signal row2x : unsigned(9 downto 0);
+  signal ucol : unsigned(9 downto 0);
+  signal urow : unsigned(9 downto 0);
+  signal tileaddress : std_logic_vector(10 downto 0);
+  signal char : std_logic_vector(7 downto 0);
+  signal char_row : std_logic_vector(7 downto 0);
+
+begin
+
+  -- 8x8 bitmap is upscaled 2x
+  ucol <= to_unsigned(column, 10);
+  urow <= to_unsigned(row, 10);
+  col2x <= shift_right(urow, 1);
+  row2x <= shift_right(ucol, 1);
+
+
+end;
+ 
diff --git a/testsuite/synth/bug01/testsuite.sh b/testsuite/synth/bug01/testsuite.sh
new file mode 100755
index 000000000..423496718
--- /dev/null
+++ b/testsuite/synth/bug01/testsuite.sh
@@ -0,0 +1,9 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth display.vhdl -e display > syn_display.vhdl
+analyze syn_display.vhdl
+clean
+
+echo "Test successful"
-- 
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