From 23744bad75edd84f9f4e20a9c29a96a85ee4b810 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sun, 23 Apr 2023 08:51:28 +0200
Subject: testsuite/synth: add a test for external names

---
 testsuite/synth/external01/externalerr01.vhdl | 58 +++++++++++++++++++++++++++
 testsuite/synth/external01/testsuite.sh       |  2 +
 2 files changed, 60 insertions(+)
 create mode 100644 testsuite/synth/external01/externalerr01.vhdl

diff --git a/testsuite/synth/external01/externalerr01.vhdl b/testsuite/synth/external01/externalerr01.vhdl
new file mode 100644
index 000000000..91490ac6b
--- /dev/null
+++ b/testsuite/synth/external01/externalerr01.vhdl
@@ -0,0 +1,58 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity externalerr01_sub is
+  port (clk : std_logic;
+        rst : std_logic;
+        a : std_logic_vector(7 downto 0);
+        o : out std_logic_vector(7 downto 0));
+end externalerr01_sub;
+
+architecture behav of externalerr01_sub is
+  signal accum : std_logic_vector(7 downto 0);
+begin
+  process (clk) is
+  begin
+    if rising_edge(clk) then
+      if rst = '1' then
+        accum <= (others => '0');
+      else
+        accum <= std_logic_vector(unsigned(accum) + unsigned(a));
+      end if;
+    end if;
+  end process;
+
+  process (clk) is
+  begin
+    if rising_edge(clk) then
+      if rst = '1' then
+        o <= (others => '0');
+      else
+        o <= accum;
+      end if;
+    end if;
+  end process;
+end behav;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity externalerr01 is
+  port (clk : std_logic;
+        rst : std_logic;
+        a : std_logic_vector(7 downto 0);
+        accum : out std_logic_vector(7 downto 0);
+        o : out std_logic_vector(7 downto 0));
+end externalerr01;
+
+architecture behav of externalerr01 is
+begin
+  dut : entity work.externalerr01_sub
+    port map (clk => clk,
+              rst => rst,
+              a => a,
+              o => o);
+  accum <= << signal .externalerr01.dut.accum : bit_vector(7 downto 0) >>;
+end behav;
diff --git a/testsuite/synth/external01/testsuite.sh b/testsuite/synth/external01/testsuite.sh
index 964831634..1b3dfc367 100755
--- a/testsuite/synth/external01/testsuite.sh
+++ b/testsuite/synth/external01/testsuite.sh
@@ -7,4 +7,6 @@ GHDL_SYNTH_FLAGS=--keep-hierarchy=no
 
 synth_only external01
 
+synth_failure externalerr01.vhdl -e
+
 echo "Test successful"
-- 
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