From 1b78b16bd6ffde3cf5ab83f5e3cb65d9dfc09b85 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Sun, 14 Jul 2019 07:04:56 +0200 Subject: ghdlsynth: check top entity can be a top entity. --- src/ghdldrv/ghdlcomp.adb | 2 +- src/ghdldrv/ghdlsynth.adb | 52 ++++++++++++++++++++++++------------- src/vhdl/translate/trans-chap12.adb | 2 +- src/vhdl/vhdl-configuration.adb | 5 ++-- src/vhdl/vhdl-configuration.ads | 3 ++- 5 files changed, 41 insertions(+), 23 deletions(-) diff --git a/src/ghdldrv/ghdlcomp.adb b/src/ghdldrv/ghdlcomp.adb index 452acaa75..a20ff932a 100644 --- a/src/ghdldrv/ghdlcomp.adb +++ b/src/ghdldrv/ghdlcomp.adb @@ -338,7 +338,7 @@ package body Ghdlcomp is (Get_Block_Specification (Get_Block_Configuration (Conf_Unit))); Entity : constant Iir := Vhdl.Utils.Get_Entity (Arch); begin - Vhdl.Configuration.Check_Entity_Declaration_Top (Entity); + Vhdl.Configuration.Check_Entity_Declaration_Top (Entity, True); if Nbr_Errors > 0 then raise Compilation_Error; end if; diff --git a/src/ghdldrv/ghdlsynth.adb b/src/ghdldrv/ghdlsynth.adb index cf9b2dc24..429d1ab55 100644 --- a/src/ghdldrv/ghdlsynth.adb +++ b/src/ghdldrv/ghdlsynth.adb @@ -31,6 +31,7 @@ with Vhdl.Std_Package; with Vhdl.Canon; with Vhdl.Configuration; with Vhdl.Annotations; +with Vhdl.Utils; with Synthesis; with Netlists; use Netlists; @@ -97,6 +98,9 @@ package body Ghdlsynth is E_Opt : Integer; Opt_Arg : Natural; Config : Iir; + Top : Iir; + Prim_Id : Name_Id; + Sec_Id : Name_Id; begin -- If the '-e' switch is present, there is a list of files. E_Opt := Args'First - 1; @@ -128,27 +132,39 @@ package body Ghdlsynth is -- Elaborate if E_Opt = Args'Last then -- No unit. - declare - Top : Node; - begin - Top := Vhdl.Configuration.Find_Top_Entity (Libraries.Work_Library); - if Top = Null_Node then - Ghdlmain.Error ("no top unit found"); - return No_Module; - end if; - Errorout.Report_Msg (Msgid_Note, Option, No_Source_Coord, - "top entity is %i", (1 => +Top)); - Config := Vhdl.Configuration.Configure - (Get_Identifier (Top), Null_Identifier); - end; + Top := Vhdl.Configuration.Find_Top_Entity (Libraries.Work_Library); + if Top = Null_Node then + Ghdlmain.Error ("no top unit found"); + return No_Module; + end if; + Errorout.Report_Msg (Msgid_Note, Option, No_Source_Coord, + "top entity is %i", (1 => +Top)); + Prim_Id := Get_Identifier (Top); + Sec_Id := Null_Identifier; else - Common_Compile_Elab - ("--synth", Args (E_Opt + 1 .. Args'Last), Opt_Arg, Config); + Extract_Elab_Unit ("--synth", Args (E_Opt + 1 .. Args'Last), Opt_Arg, + Prim_Id, Sec_Id); + if Opt_Arg <= Args'Last then + Ghdlmain.Error ("extra options ignored"); + return No_Module; + end if; end if; - if Opt_Arg <= Args'Last then - Ghdlmain.Error ("extra options ignored"); - end if; + Config := Vhdl.Configuration.Configure (Prim_Id, Sec_Id); + + -- Check (and possibly abandon) if entity can be at the top of the + -- hierarchy. + declare + Conf_Unit : constant Iir := Get_Library_Unit (Config); + Arch : constant Iir := Get_Named_Entity + (Get_Block_Specification (Get_Block_Configuration (Conf_Unit))); + Entity : constant Iir := Vhdl.Utils.Get_Entity (Arch); + begin + Vhdl.Configuration.Check_Entity_Declaration_Top (Entity, False); + if Nbr_Errors > 0 then + raise Compilation_Error; + end if; + end; -- Annotate all units. Vhdl.Annotations.Annotate (Vhdl.Std_Package.Std_Standard_Unit); diff --git a/src/vhdl/translate/trans-chap12.adb b/src/vhdl/translate/trans-chap12.adb index 9fda541a8..f153251f6 100644 --- a/src/vhdl/translate/trans-chap12.adb +++ b/src/vhdl/translate/trans-chap12.adb @@ -544,7 +544,7 @@ package body Trans.Chap12 is (Get_Block_Specification (Get_Block_Configuration (Config_Lib))); -- Be sure the entity can be at the top of a design. - Check_Entity_Declaration_Top (Entity); + Check_Entity_Declaration_Top (Entity, True); -- If all design units are loaded, late semantic checks can be -- performed. diff --git a/src/vhdl/vhdl-configuration.adb b/src/vhdl/vhdl-configuration.adb index 573a0b435..25e29b305 100644 --- a/src/vhdl/vhdl-configuration.adb +++ b/src/vhdl/vhdl-configuration.adb @@ -685,7 +685,8 @@ package body Vhdl.Configuration is return Top; end Configure; - procedure Check_Entity_Declaration_Top (Entity : Iir_Entity_Declaration) + procedure Check_Entity_Declaration_Top + (Entity : Iir_Entity_Declaration; Enable_Override : Boolean) is Has_Error : Boolean := False; @@ -747,7 +748,7 @@ package body Vhdl.Configuration is El := Get_Generic_Chain (Entity); while El /= Null_Iir loop if Get_Default_Value (El) = Null_Iir then - if not Allow_Generic_Override (El) then + if not (Enable_Override and Allow_Generic_Override (El)) then Error (El, "(%n has no default value)", +El); end if; end if; diff --git a/src/vhdl/vhdl-configuration.ads b/src/vhdl/vhdl-configuration.ads index c6a5105cd..8cadad8fc 100644 --- a/src/vhdl/vhdl-configuration.ads +++ b/src/vhdl/vhdl-configuration.ads @@ -51,7 +51,8 @@ package Vhdl.Configuration is -- ENTITY has no generics or all generics have a default expression -- ENTITY has no ports or all ports type are constrained. -- If not, emit a elab error message. - procedure Check_Entity_Declaration_Top (Entity : Iir_Entity_Declaration); + procedure Check_Entity_Declaration_Top + (Entity : Iir_Entity_Declaration; Enable_Override : Boolean); -- Use heuritics to find the top entity in FROM (either a library or -- a design file): mark all instantiated units and return the unmarked -- cgit v1.2.3