From 1a789146110f65b78df8595fb28d62cf79ab0b1b Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Mon, 13 Jun 2022 18:44:08 +0200
Subject: testsuite/synth: add a test for #2092

---
 testsuite/synth/issue2092/testcase.vhdl | 25 +++++++++++++++++++++++++
 testsuite/synth/issue2092/testsuite.sh  | 11 +++++++++++
 2 files changed, 36 insertions(+)
 create mode 100644 testsuite/synth/issue2092/testcase.vhdl
 create mode 100755 testsuite/synth/issue2092/testsuite.sh

diff --git a/testsuite/synth/issue2092/testcase.vhdl b/testsuite/synth/issue2092/testcase.vhdl
new file mode 100644
index 000000000..a2659bad2
--- /dev/null
+++ b/testsuite/synth/issue2092/testcase.vhdl
@@ -0,0 +1,25 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity testcase is
+    port(
+        rst : in std_ulogic;
+        clk : in std_ulogic
+    );
+end entity testcase;
+
+architecture rtl of testcase is
+
+    component testcase2 port (
+        rst : in std_ulogic;
+        clk : in std_ulogic
+    );
+    end component;
+
+begin
+    testcase2_0: testcase2
+        port map (
+            clk => clk,
+            rst => rst
+        );
+end architecture rtl;
diff --git a/testsuite/synth/issue2092/testsuite.sh b/testsuite/synth/issue2092/testsuite.sh
new file mode 100755
index 000000000..1d1fb9466
--- /dev/null
+++ b/testsuite/synth/issue2092/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth --out=verilog testcase.vhdl -e > syn_testcase.v
+
+if grep "module testcase2" syn_testcase.v; then
+  exit 1
+fi
+
+echo "Test successful"
-- 
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