From 14ba70a30d5ce4395eea8c668bcafc85790b5247 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Tue, 8 Oct 2019 06:28:45 +0200
Subject: testsuite/synth: add testcase for #964

---
 testsuite/synth/issue964/ent.vhdl     | 28 ++++++++++++++++++
 testsuite/synth/issue964/tb_ent.vhdl  | 55 +++++++++++++++++++++++++++++++++++
 testsuite/synth/issue964/testsuite.sh | 16 ++++++++++
 3 files changed, 99 insertions(+)
 create mode 100644 testsuite/synth/issue964/ent.vhdl
 create mode 100644 testsuite/synth/issue964/tb_ent.vhdl
 create mode 100755 testsuite/synth/issue964/testsuite.sh

diff --git a/testsuite/synth/issue964/ent.vhdl b/testsuite/synth/issue964/ent.vhdl
new file mode 100644
index 000000000..abed11a80
--- /dev/null
+++ b/testsuite/synth/issue964/ent.vhdl
@@ -0,0 +1,28 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ent is
+    port (
+        clk : in std_logic;
+        reset : in std_logic;
+        enable : in std_logic;
+        q : out std_logic
+    );
+end;
+
+architecture a of ent is
+    signal s : std_logic;
+begin
+    process(clk, reset)
+    begin
+        if reset = '1' then
+            s <= '0';
+        elsif enable /= '1' then
+            -- [nothing]
+        elsif rising_edge(clk) then
+            s <= not s;
+        end if;
+    end process;
+
+    q <= s;
+end;
diff --git a/testsuite/synth/issue964/tb_ent.vhdl b/testsuite/synth/issue964/tb_ent.vhdl
new file mode 100644
index 000000000..76cbf8b31
--- /dev/null
+++ b/testsuite/synth/issue964/tb_ent.vhdl
@@ -0,0 +1,55 @@
+entity tb_ent is
+end tb_ent;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_ent is
+  signal clk : std_logic;
+  signal dout : std_logic;
+  signal enable : std_logic;
+  signal reset : std_logic;
+begin
+  dut: entity work.ent
+    port map (
+      enable => enable,
+      reset => reset,
+      q => dout,
+      clk => clk);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    enable <= '1';
+    reset <= '1';
+    pulse;
+    assert dout = '0' severity failure;
+
+    enable <= '1';
+    reset <= '0';
+    pulse;
+    assert dout = '1' severity failure;
+
+    pulse;
+    assert dout = '0' severity failure;
+
+    pulse;
+    assert dout = '1' severity failure;
+
+    enable <= '0';
+    pulse;
+    assert dout = '1' severity failure;
+
+    enable <= '1';
+    pulse;
+    assert dout = '0' severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue964/testsuite.sh b/testsuite/synth/issue964/testsuite.sh
new file mode 100755
index 000000000..e30a741e0
--- /dev/null
+++ b/testsuite/synth/issue964/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in ent; do
+    analyze $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t --ieee-asserts=disable-at-0
+    clean
+done
+
+echo "Test successful"
-- 
cgit v1.2.3