From 13f04d9fbf5ca617b9f0cef692556c5639b0033e Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Mon, 22 Jul 2019 03:30:41 +0200
Subject: synth: remove bounds (unused) for ports.

---
 src/synth/netlists-builders.adb | 6 ++----
 src/synth/netlists.adb          | 4 +---
 src/synth/netlists.ads          | 4 ----
 src/synth/synth-insts.adb       | 3 +--
 4 files changed, 4 insertions(+), 13 deletions(-)

diff --git a/src/synth/netlists-builders.adb b/src/synth/netlists-builders.adb
index 5457a8514..7274fc0a6 100644
--- a/src/synth/netlists-builders.adb
+++ b/src/synth/netlists-builders.adb
@@ -27,16 +27,14 @@ package body Netlists.Builders is
    begin
       return (Name => New_Sname_Artificial (Get_Identifier (Id)),
               W => W,
-              Dir => Port_In,
-              Left | Right => 0);
+              Dir => Port_In);
    end Create_Input;
 
    function Create_Output (Id : String; W : Width := 0) return Port_Desc is
    begin
       return (Name => New_Sname_Artificial (Get_Identifier (Id)),
               W => W,
-              Dir => Port_Out,
-              Left | Right => 0);
+              Dir => Port_Out);
    end Create_Output;
 
    procedure Create_Dyadic_Module (Design : Module;
diff --git a/src/synth/netlists.adb b/src/synth/netlists.adb
index f6180f715..edc66dbf8 100644
--- a/src/synth/netlists.adb
+++ b/src/synth/netlists.adb
@@ -831,9 +831,7 @@ begin
 
    Port_Desc_Table.Append ((Name => No_Sname,
                             W => 0,
-                            Dir => Port_In,
-                            Left => 0,
-                            Right => 0));
+                            Dir => Port_In));
    pragma Assert (Port_Desc_Table.Last = No_Port_Desc_Idx);
 
    Param_Desc_Table.Append ((Name => No_Sname,
diff --git a/src/synth/netlists.ads b/src/synth/netlists.ads
index 6cf021ec1..56393ac28 100644
--- a/src/synth/netlists.ads
+++ b/src/synth/netlists.ads
@@ -151,10 +151,6 @@ package Netlists is
 
       --  Direction.
       Dir : Port_Kind;
-
-      --  For a bus: left and right bounds of the bus, ie [L:R].
-      Left : Int32;
-      Right : Int32;
    end record;
 
    type Port_Desc_Array is array (Port_Idx range <>) of Port_Desc;
diff --git a/src/synth/synth-insts.adb b/src/synth/synth-insts.adb
index 0adb9f28b..ec63d2d1d 100644
--- a/src/synth/synth-insts.adb
+++ b/src/synth/synth-insts.adb
@@ -78,8 +78,7 @@ package body Synth.Insts is
             Idx := Idx + 1;
             Ports (Idx) := (Name => Name,
                             W => Wd,
-                            Dir => Dir,
-                            Left | Right => 0);
+                            Dir => Dir);
          when others =>
             raise Internal_Error; --  TODO
       end case;
-- 
cgit v1.2.3