From 0926686937d3c673f46cd0d5c770a7fd4744a47d Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Tue, 9 Jul 2019 05:15:27 +0200
Subject: Add testcase for #864

---
 testsuite/gna/issue864/mwe.vhdl     | 39 ++++++++++++++++++++++++++++++++++++
 testsuite/gna/issue864/mwe2.vhdl    | 40 +++++++++++++++++++++++++++++++++++++
 testsuite/gna/issue864/testsuite.sh | 11 ++++++++++
 3 files changed, 90 insertions(+)
 create mode 100644 testsuite/gna/issue864/mwe.vhdl
 create mode 100644 testsuite/gna/issue864/mwe2.vhdl
 create mode 100755 testsuite/gna/issue864/testsuite.sh

diff --git a/testsuite/gna/issue864/mwe.vhdl b/testsuite/gna/issue864/mwe.vhdl
new file mode 100644
index 000000000..bf8be1b10
--- /dev/null
+++ b/testsuite/gna/issue864/mwe.vhdl
@@ -0,0 +1,39 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity a is
+  port (
+    a_in : IN std_logic;
+    a_out : OUT std_logic
+  );
+end entity a;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity b is
+  port (
+    b_in : IN std_logic;
+    b_out : OUT std_logic
+  );
+end entity b;
+
+architecture rtl of a is
+begin
+  process (a_in)
+  begin
+    a_out <= a_in;
+  end process;
+end architecture rtl;
+
+architecture rtl of b is 
+  component a
+    port (
+      a_in : IN std_logic;
+      a_out : OUT std_logic
+    );
+  end component;
+
+  for a0 : a;
+begin
+end architecture rtl;
diff --git a/testsuite/gna/issue864/mwe2.vhdl b/testsuite/gna/issue864/mwe2.vhdl
new file mode 100644
index 000000000..fe6507ca5
--- /dev/null
+++ b/testsuite/gna/issue864/mwe2.vhdl
@@ -0,0 +1,40 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity a is
+  port (
+    a_in : IN std_logic;
+    a_out : OUT std_logic
+  );
+end entity a;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity b is
+  port (
+    b_in : IN std_logic;
+    b_out : OUT std_logic
+  );
+end entity b;
+
+architecture rtl of a is
+begin
+  process (a_in)
+  begin
+    a_out <= a_in;
+  end process;
+end architecture rtl;
+
+architecture rtl of b is 
+  component a
+    port (
+      a_in : IN std_logic;
+      a_out : OUT std_logic
+    );
+  end component;
+
+  for a0 : a;
+begin
+  a0: a port map (a_in => b_in, a_out => b_out);
+end architecture rtl;
diff --git a/testsuite/gna/issue864/testsuite.sh b/testsuite/gna/issue864/testsuite.sh
new file mode 100755
index 000000000..22d3edd23
--- /dev/null
+++ b/testsuite/gna/issue864/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze_failure mwe.vhdl
+clean
+
+analyze_failure mwe2.vhdl
+clean
+
+echo "Test successful"
-- 
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